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HD404459 Series
Rev. 6.0 Sept. 1998 Description
The HD404459 Series is a member of the 4-bit HMCS400-series microcomputers with large-capacity memory and architecture providing high program productivity. Each microcomputer has a 32-kHz oscillator for clock, low-voltage (1.8 V) operating mode, and four low-power dissipation modes. The HD404459 Series includes three chips: the HD404458 with an 8-kword ROM; the HD404459 with a 16-kword ROM; and the HD4074459 with a 16-kword PROM (ZTATTM version). The HD4074459 is a PROM version (ZTATTM microcomputer). A program can be written to the PROM by a PROM writer, thus dramatically shortening system development periods and turnaround time (ZTAT TM versions are 27256-compatible). ZTAT TM: Zero Turn Around Time ZTAT is a trademark of Hitachi, Ltd.
Features
* 8,192-word x 10-bit ROM (HD404458) 16,384-word x 10-bit ROM (HD404459 and HD4074459) * 512-digit x 4-bit RAM (HD404458) 768-digit x 4-bit RAM (HD404459 and HD4074459) * 56 I/O pins, including seven input pins * Four timer/counters * 1-channel x 8-bit input capture circuit * Three timer outputs (including two PWM outputs) * Two event counter inputs (including one double-edge function) * 8-bit clock-synchronous serial interface * Eight wakeup inputs * Four-channel voltage comparator (external or internal reference power supply can be selected) * Built-in oscillators Main clock: 4-MHz ceramic or crystal oscillator (an external clock is also possible) Subclock: 32.768-kHz crystal
HD404459 Series
* Ten interrupt sources Five by external sources, including two double-edge function Five by internal sources * Subroutine stack up to 16 levels, including interrupts * Four low-power dissipation modes (transition time shortened) Stop mode Standby mode Watch mode Subactive mode (optional) * One external input for transition from stop mode to active mode * Instruction cycle time For HD404458/HD404459: 1, 2, 4, 8 s (fOSC = 4 MHz; 1/4, 1/8, 1/16, 1/32 division ratio) For HD4074459: 1, 2, 4, 8 s (fOSC = 4 MHz; 1/4, 1/8, 1/16, 1/32 division ratio; power voltage of 2.7 V or higher) 2, 4, 8, 16 s (fOSC = 2 MHz; 1/4, 1/8, 1/16, 1/32 division ratio; power voltage of 2.2 V or higher) * Two general operating conditions MCU or PROM mode for HD4074459 MCU mode only for HD404458/HD404459
Ordering Information
Type Mask ROM Product Name HD404458 HD404459 ZTATTM HD4074459 Model Name HD404458H HD404459H HD4074459H ROM (Words) 8,192 16,384 16,384 RAM (Digits) 512 768 768 Package 64-pin plastic QFP (FP-64A) 64-pin plastic QFP (FP-64A) 64-pin plastic QFP (FP-64A)
2
HD404459 Series
Pin Arrangement
R93/VCref R92 R91 R90 R83 R82 R81 R80 R73 R72 R71 R70 R63 (WU7) R62 (WU6) R61 (WU5) R60 (WU4)
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50
RA0/COMP0 RA1/COMP1 RA2/COMP2 RA3/COMP3 TEST OSC1 OSC2 GND X2 X1 RESET D0 D1 D2 D3 D4
49
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
FP-64A
R53 (WU3) R52 (WU2) R51 (WU1) R50 (WU0) R43/SO R42/SI R41/SCK R40/EVND R33/EVNB R32/TOD R31/TOC R30/TOB R23 R22 R21 R20
D5 D6 D7 D8 D9 D10 D11/STOPC VCC R00/INT0 R01/INT1 R02/INT2 R03/INT3 R10 R11 R12 R13
3
HD404459 Series
Pin Description
Pin Number Item Symbol FP-64A 24 8 5 11 6 I I I I/O Function Power voltage Ground Used for factory testing only: Connect this pin to V CC Resets the MCU Input/output pins for the internal oscillator circuit: Connect them to a ceramic, crystal, or connect only OSC 1 to an external oscillator circuit
Power supply VCC GND Test Reset Oscillator TEST RESET OSC 1
OSC 2 X1
7 10
O I Used for a 32.768-kHz crystal for clock purposes. If not to be used, fix the X1 pin to V CC and leave the X2 pin open.
X2 Ports D0-D 9 D10, D11 R0 0-R9 3 RA 0-RA 3 Interrupts INT0, INT1, INT2, INT3, WU0-WU7 Stop clear Serial interface STOPC SCK SI SO Timers TOB, TOC, TOD EVNB, EVND Voltage comparator COMP0 - COMP3 VC ref
9 12-21 22, 23 25-64 1-4 25-28, 45-52
O I/O I I/O I I Input/output pins addressable by individual bits Input pins addressable by individual bits Input/output pins addressable in 4-bit units. The R93 port is an input-only pin. Input pins addressable in 4-bit units Input pins for external interrupts
23 42 43 44 37-39
I I/O I O O
Input pin for transition from stop mode to active mode Serial clock input/output pin Serial receive data input pin Serial transmit data output pin Timer output pins
40, 41
I
Event count input pins
1-4
I
Analog input pins for voltage comparator
64
I
Standard voltage pin for inputting the threshold voltage of analog input pins
4
HD404459 Series
Block Diagram
RESET TEST STOPC OSC 1 OSC 2 X1 X2 VCC GND
System control
INT 0 INT 1 INT 2 INT 3 WU0 to WU7 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D 10 D 11 R0 0 R0 1 R0 2 R0 3 R1 0 R1 1 R1 2 R1 3 R2 0 R2 1 R2 2 R2 3 R3 0 R3 1 R3 2 R3 3 R4 0 R4 1 R4 2 R4 3 R5 0 R5 1 R5 2 R5 3 R6 0 R6 1 R6 2 R6 3 R7 0 R7 1 R7 2 R7 3 R8 0 R8 1 R8 2 R8 3 R9 0 R9 1 R9 2 R9 3 RA 0 RA 1 RA 2 RA 3
External interrupt
RAM (512 x 4 bits) (768 x 4 bits)
D port RA port R9 port R8 port R7 port R6 port R5 port R4 port R3 port R2 port R1 port R0 port
W (2 bits) Timer A X (4 bits)
EVNB TOB
Timer B
SPX (4 bits) Y (4 bits)
TOC
Timer C
Internal data bus
EVND TOD SI SO SCK VCref COMP0 COMP1 COMP2 COMP3
Timer D
Serial interface
Internal address bus
SPY (4 bits)
Comparator
ALU CPU ST CA (1 bit) (1 bit) A (4 bits) B (4 bits) SP (10 bits)
Instruction decoder
PC (14 bits)
ROM (8,192 x 10 bits) (16,384 x 10 bits)
5
HD404459 Series
Memory Map
ROM Memory Map See the ROM memory map of figure 1. Vector Address Area ($0000-$000F): Reserved for JMPL instructions that branch to the start addresses of the reset and interrupt routines. After MCU reset or an interrupt, program execution continues from the vector address. Zero-Page Subroutine Area ($0000-$003F): Reserved for subroutines. The program branches to a subroutine in this area in response to the CAL instruction. Pattern Area ($0000-$0FFF): Contains ROM data that can be referenced with the P instruction. Program Area ($0000-$1FFF for HD404458, $0000-$3FFF for HD404459/HD4074459): Used for program coding.
$0000 Vector address $000F $0010 Zero-page subroutine (64 words) $003F $0040 Pattern (4,096 words) $0FFF $1000 HD404458 program (8,192 words) $1FFF $2000
$0000 $0002 $0003 $0004 $0005 $0006 $0007 $0008 $0009
JMPL instruction $0001 (jump to RESET, STOPC routine) JMPL instruction (jump to INT0 routine) JMPL instruction (jump to INT1 routine) JMPL instruction (jump to timer D routine) JMPL instruction (jump to timer A, INT2 routine) JMPL instruction (jump to timer B, INT3 routine) JMPL instruction (jump to timer C, serial routine) JMPL instruction (jump to wakeup routine)
$000A $000B $000C $000D $000E $000F
HD404459, HD4074459 program (16,384 words)
$3FFF
Figure 1 ROM Memory Map
6
HD404459 Series
RAM Memory Map The HD404458 MCU contains a 512-digit x 4-bit RAM area. The HD404459 and HD4074459 MCUs contain 768-digit x 4-bit RAM areas. Both of these RAM areas consist of a memory register area, a data area, and a stack area. In addition, an interrupt control bits area, special register area, and register flag area are mapped onto the same RAM memory space labeled as the RAM-mapped register area. See the RAM memory map of figure 2. RAM-Mapped Register Area ($000-$03F): * Interrupt control bits area ($000-$003) This area is used for interrupt control bits (figure 3). These bits can be accessed only by RAM bit manipulation instructions (SEM/SEMD, REM/REMD, and TM/TMD). However, note that not all the instructions can be used for each bit. For limitations on using the instructions, refer to figure 4. * Special function register area ($004-$01F, $024-$03F) This area is used as mode registers and data registers for external interrupts, serial interface, timer/counters, and as data control registers for I/O ports. See figures 2 and 5. These registers can be classified into three types: write-only (W), read-only (R), and read/write (R/W). RAM bit manipulation instructions cannot be used for these registers. * Register flag area ($020-$023) This area is used for the DTON, WDON, and other register flags and interrupt control bits (figure 3). These bits can be accessed only by RAM bit manipulation instructions (SEM/SEMD, REM/REMD, and TM/TMD). However, note that not all the instructions can be used for each bit. For limitations on using the instructions, refer to figure 4. Memory Register (MR) Area ($040-$04F): Consisting of 16 addresses, this area (MR0-MR15) can be accessed by register-register instructions (LAMR and XMRA). See figure 6. Data Area ($050-$1FF for HD404458, $050-$2FF for HD404459/HD4074459) Stack Area ($3C0-$3FF): Used for saving the contents of the program counter (PC), status flag (ST), and carry flag (CA) at subroutine call (CAL or CALL instruction) and for interrupts. This area can be used as a 16-level nesting subroutine stack in which one level requires four digits. See figure 6 for the data to be saved and the save conditions. The program counter is restored by either the RTN or RTNI instruction, but the status and carry flags can only be restored by the RTNI instruction. Any unused space in this area can be used for data storage.
7
HD404459 Series
0 RAM-mapped register 64 80 HD404458 Data (432 digits) $040 $050 $000 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 Interrupt control bits area (PMRA) (SMRA) (SRL) (SRU) (TMA) (TMB1) (TRBL/TWBL) Timer B (TRBU/TWBU) (MIS) Miscellaneous register (TMC1) Timer mode register C1 (TRCL/TWCL) Timer C (TRCU/TWCU) (TMD1) Timer mode register D1 (TRDL/TWDL) Timer D (TRDU/TWDU) (TMB2) Timer mode register B2 (TMC2) Timer mode register C2 (TMD2) Timer mode register D2 (CCR) Comparator control register (CER) Comparator enable register (WSR) Wakeup select register Port mode register A Serial mode register A Serial data register lower Serial data register upper Timer mode register A Timer mode register B1 W W R/W R/W W W R/W R/W W W R/W R/W W R/W R/W R/W R/W R/W W R/W R $000 $001 $002 $003 $004 $005 $006 $007 $008 $009 $00A $00B $00C $00D $00E $00F $010 $011 $012 $013 $014 $015 $016 $017 $018 $019 $01A $01B $01C $01D $01E $01F $020 $021 $022 $023 $024 $025 $026 $027 $028 $029 $02A $02B $02C $02D $02E $02F $030 $031 $032 $033 $034 $035 $036 $037 $038 $039 $03A $03B $03C $03D $03E $03F $00A $00B $00E $00F $011 $012
Memory register (MR)
*
512 HD404459, HD4074459 Data (688 digits)
$200
768 Not used
$300
960 Stack (64 digits) 1023
$3C0
$3FF
Not used
Note: * Two registers are mapped onto the same address ($00A, $00B, $00E, $00F, $011, and $012). R: Read only W: Write only R/W: Read/write
Register flag area Port mode register B Port mode register C Detection edge select register 1 Detection edge select register 2 Serial mode register B System clock select register 1 System clock select register 2 Not used Port D0 to D3 DCR Port D4 to D7 DCR Port D8 to D9 DCR Not used Port R0 DCR Port R1 DCR Port R2 DCR Port R3 DCR Port R4 DCR Port R5 DCR Port R6 DCR Port R7 DCR Port R8 DCR Port R9 DCR (PMRB) (PMRC) (ESR1) (ESR2) (SMRB) (SSR1) (SSR2) (DCD0) (DCD1) (DCD2) (DCR0) (DCR1) (DCR2) (DCR3) (DCR4) (DCR5) (DCR6) (DCR7) (DCR8) (DCR9) W W W W W W W W W W W W W W W W W W W W
Not used
10 Timer read register B lower (TRBL) 11 Timer read register B upper (TRBU) 14 Timer read register C lower (TRCL) 15 Timer read register C upper (TRCU) 17 Timer read register D lower (TRDL) 18 Timer read register D upper (TRDU)
R R R R R R
Timer write register B lower (TWBL) Timer write register B upper (TWBU) Timer write register C lower (TWCL) Timer write register C upper (TWCU) Timer write register D lower (TWDL) Timer write register D upper (TWDU)
W W W W W W
Figure 2 RAM Memory Map
8
HD404459 Series
Interrupt control bits area
Bit 3
0
Bit 2
Bit 1
Bit 0
IE (Interrupt enable flag)
$000
IM0 (IM of INT0)
IF0 (IF of INT0)
RSP (Reset SP bit)
1
IMTD (IM of timer D)
IMTB (IM of timer B)
IMWU (IM of wakeup)
IFTD (IF of timer D) IFTB (IF of timer B)
IFWU (IF of wakeup)
IM1 (IM of INT1)
IMTA (IM of timer A) IMTC (IM of timer C)
IF1 (IF of INT1)
IFTA (IF of timer A)
IFTC (IF of timer C)
$001
2
$002
3
$003
Register flag area
Bit 3
32
DTON (Direct transfer on flag)
Bit 2
CMSF (Comparator start flag)
Bit 1
WDON (Watchdog on flag)
Bit 0
LSON (Low speed on flag) $020
33
RAME (RAM enable flag)
Not used
ICEF (Input capture error flag)
ICSF (Input capture status flag)
$021
34
IM3 (IM of INT3)
Not used
IF3 (IF of INT3)
Not used
IM2 (IM of INT2)
IMS (IM of serial)
IF2 (IF of INT2)
IFS (IF of serial)
$022
35
$023
IF: Interrupt request flag IM: Interrupt mask SP: Stack pointer
Figure 3 Configuration of Interrupt Control Bits and Register Flag Areas
SEM/SEMD IE IM LSON IF ICSF ICEF RAME RSP WDON CMSF DTON Not used Allowed REM/REMD Allowed TM/TMD Allowed
Not executed Not executed Allowed Allowed Not executed in active mode Used in subactive mode Not executed
Allowed Allowed Not executed Inhibited Allowed Not executed
Allowed Inhibited Inhibited Allowed Allowed Inhibited
Note: WDON is reset by MCU reset or by STOPC enable for stop mode cancellation. The REM or REMD instuction must not be executed for CMSF during comparator operation. DTON is always reset in active mode. If the TM or TMD instruction is executed for the inhibited bits or non-existing bits, the value in ST becomes undefined.
Figure 4 Usage Limitations of RAM Bit Manipulation Instructions
9
HD404459 Series
Bit 3 $000 Interrupt control bits area $003 PMRA $004 SMRA $005 SRL $006 SRU $007 TMA $008 TMB1 $009 TRBL/TWBL $00A TRBU/TWBU $00B MIS $00C TMC1 $00D TRCL/TWCL$00E TRCU/TWCU $00F TMD1 $010 TRDL/TWDL $011 TRDU/TWDU $012 TMB2 $013 TMC2 $014 TMD2 $015 CCR $016 CER $017 WSR $018 Pull-up MOS control Auto-reload on/off Timer-A/timer-base Auto-reload on/off Bit 2 Bit 1 Bit 0
Not used R41/SCK
Not used
R42/SI Serial transmit clock speed selection
R4 3 /SO
Serial data register (lower digit) Serial data register (upper digit) Clock source selection (timer A) Clock source selection (timer B) Timer B register (lower digit) Timer B register (upper digit) SO PMOS control Interrupt frame period selection Clock source selection (timer C)
Timer C register (lower digit) Timer C register (upper digit) Auto-reload on/off Clock source selection (timer D) Timer D register (lower digit) Timer D register (upper digit) Timer B output mode selection Not used Timer C output mode selection Timer D output mode selection Internal reference voltage level selection Reference power supply selection COMP0 to COMP3 selection WU6 enable WU5 to WU4 enable WU3 to WU0 enable
Not used Not used Input capture selection Voltage comparison result WU7 enable
Not used
$020 Register flag area $023 PMRB $024 PMRC $025 ESR1 $026 ESR2 $027 SMRB $028 SSR1 $029 SSR2 $02A DCD0 $02C DCD1 $02D DCD2 $02E DCR0 $030 DCR1 $031 DCR2 $032 DCR3 $033 DCR4 $034 DCR5 $035 DCR6 $036 DCR7 $037 DCR8 $038 DCR9 $039
R03 /INT 3
R02 /INT 2
R01 /INT 1
R00 /INT 0
Not used D11 /STOPC INT 3 detection edge selection EVND detection edge selection Not used 32-kHz oscillation stop Not used Port D3 DCR Port D7 DCR Not used Port R0 3 DCR Port R1 3 DCR Port R2 3 DCR Port R3 3 DCR Port R4 3 DCR Port R5 3 DCR Port R6 3 DCR Port R7 3 DCR Port R8 3 DCR Not used
R40 /EVND R33 /EVNB INT 2 detection edge selection Not used Not used
Not used SO output level control in idle states Serial clock source selection Not used 32-kHz oscillation division ratio selection 32-kHz oscillation sampling selection OSC division ratio selection Not used Not used Port D2 DCR Port D6 DCR Not used Not used Port R0 2 DCR Port R1 2 DCR Port R2 2 DCR Port R3 2 DCR Port R4 2 DCR Port R5 2 DCR Port R6 2 DCR Port R7 2 DCR Port R8 2 DCR Port R9 2 DCR Port R0 1 DCR Port R1 1 DCR Port R2 1 DCR Port R3 1 DCR Port R4 1 DCR Port R5 1 DCR Port R6 1 DCR Port R7 1 DCR Port R8 1 DCR Port R9 1 DCR Port R0 0 DCR Port R1 0 DCR Port R2 0 DCR Port R3 0 DCR Port R4 0 DCR Port R5 0 DCR Port R6 0 DCR Port R7 0 DCR Port R8 0 DCR Port R9 0 DCR Port D1 DCR Port D5 DCR Port D9 DCR Port D0 DCR Port D4 DCR Port D8 DCR
Not used $03F
Figure 5 Special Function Register Area
10
HD404459 Series
Memory registers MR(0) $040 64 MR(1) $041 65 MR(2) $042 66 MR(3) $043 67 MR(4) $044 68 MR(5) $045 69 MR(6) $046 70 MR(7) $047 71 MR(8) $048 72 MR(9) $049 73 MR(10) $04A 74 MR(11) $04B 75 MR(12) $04C 76 MR(13) $04D 77 MR(14) $04E 78 MR(15) $04F 79 Stack area Level 16 Level 15 Level 14 Level 13 Level 12 Level 11 Level 10 Level 9 Level 8 Level 7 Level 6 Level 5 Level 4 Level 3 Level 2 1023 Level 1 960 $3C0
Bit 3 1020 1021 1022 $3FF 1023 ST PC 10 CA PC 3
Bit 2 PC13 PC9 PC6 PC2
Bit 1 PC 12 PC 8 PC 5 PC 1
Bit 0 PC11 PC7 PC4 PC0 $3FC $3FD $3FE $3FF
PC13 -PC0 : Program counter ST: Status flag CA: Carry flag
Figure 6 Configuration of Memory Registers, Stack Area, and Stack Position
11
HD404459 Series
Functional Description
Registers and Flags The MCU has nine registers and two flags for CPU operations (figure 7).
3 Accumulator Initial value: Undefined, R/W 3 B register Initial value: Undefined, R/W (B) 1 W register Initial value: Undefined, R/W 3 X register Initial value: Undefined, R/W 3 Y register Initial value: Undefined, R/W 3 SPX register Initial value: Undefined, R/W 3 SPY register Initial value: Undefined, R/W (SPY) 0 Carry Initial value: Undefined, R/W (CA) 0 Status Program counter Initial value: 0, no R/W Stack pointer Initial value: $3FF, no R/W Initial value: 1, no R/W 13 (PC) 9 1 1 1 1 5 (SP) 0 (ST) 0 (SPX) 0 (Y) 0 (X) 0 0 (W) 0 (A) 0 0
Figure 7 Registers and Flags Accumulator (A), B Register (B): Four-bit registers used to hold the results from the arithmetic logic unit (ALU) and transfer data between memory, I/O, and other registers. W Register (W), X Register (X), Y Register (Y): Two-bit (W) and four-bit (X and Y) registers used for indirect RAM addressing. The Y register is also used for D-port addressing.
12
HD404459 Series
SPX Register (SPX), SPY Register (SPY): Four-bit registers used to supplement the X and Y registers. Carry Flag (CA): One-bit flag that stores any ALU overflow generated by an arithmetic operation. CA is affected by the SEC, REC, ROTL, and ROTR instructions. A carry is pushed onto the stack during an interrupt and popped from the stack by the RTNI instruction--but not by the RTN instruction. Status Flag (ST): One-bit flag that latches any overflow generated by an arithmetic or compare instruction, not-zero decision from the ALU, or result of a bit test. ST is used as a branch condition of the BR, BRL, CAL, and CALL instructions. The contents of ST remain unchanged until the next arithmetic, compare, or bit test instruction is executed, but become 1 after the BR, BRL, CAL, or CALL instruction is read, regardless of whether the instruction is executed or skipped. The contents of ST are pushed onto the stack during an interrupt and popped from the stack by the RTNI instruction--but not by the RTN instruction. Program Counter (PC): 14-bit binary counter that points to the ROM address of the instruction being executed. Stack Pointer (SP): Ten-bit pointer that contains the address of the stack area to be used next. The SP is initialized to $3FF by MCU reset. It is decremented by 4 when data is pushed onto the stack, and incremented by 4 when data is popped from the stack. The top four bits of the SP are fixed at 1111, so a stack can be used up to 16 levels. The SP can be initialized to $3FF also by resetting the RSP bit with the REM or REMD instruction. Reset The MCU is reset by inputting a high-level voltage to the RESET pin. At power-on or when stop mode is cancelled, RESET must be high for at least one tRC to enable the oscillator to stabilize. During operation, RESET must be high for at least two instruction cycles. See table 1 for initial values after MCU reset. Interrupts The MCU has 10 interrupt sources: four external signals (INT0 , INT1, INT2, INT 3), four timer/counters (timers A, B, C, and D), serial interface, and wakeup. An interrupt request flag (IF), interrupt mask (IM), and vector address are provided for each interrupt source, and an interrupt enable flag (IE) controls the entire interrupt process. Some vector addresses are shared by two different interrupts. They are timer A and INT2, timer B and INT3, timer C and serial interface. So the type of request that has occurred must be checked at the beginning of interrupt processing. Interrupt Control Bits and Interrupt Processing: Locations $000 to $003 and $022 to $023 in RAM are reserved for the interrupt control bits which can be accessed by RAM bit manipulation instructions. The interrupt request flag (IF) cannot be set by software. MCU reset initializes the interrupt enable flag (IE) and the IF to 0 and the interrupt mask (IM) to 1.
13
HD404459 Series
Refer to figure 8 for the block diagram of the interrupt control circuit, table 2 for interrupt priorities and vector addresses, and table 3 for interrupt processing conditions for the 10 interrupt sources. An interrupt request occurs when the IF is set to 1 and the IM is set to 0. If the IE is 1 at that point, the interrupt is processed. A priority programmable logic array (PLA) generates the vector address assigned to that interrupt source. For the interrupt processing sequence, see figure 9, and figure 10 for an interrupt processing flowchart. After an interrupt is acknowledged, the previous instruction is completed in the first cycle. The IE is reset in the second cycle, the carry, status, and program counter values are pushed onto the stack during the second and third cycles, and the program jumps to the vector address to execute the instruction in the third cycle. Program the JMPL instruction at each vector address, to branch the program to the start address of the interrupt program, and reset the IF by a software instruction within the interrupt program.
14
HD404459 Series
Table 1
Item Program counter Status flag Stack pointer Interrupt Interrupt enable flag flags/mask Interrupt request flag Interrupt mask I/O Port data register Data control register
Initial Values After MCU Reset
Abbr. (PC) (ST) (SP) (IE) (IF) (IM) (PDR) (DCD0, DCD1) (DCD2) (DCR0- DCR8) (DCR9) Port mode register A Port mode register B (PMRA) (PMRB) Initial Value $0000 1 $3FF 0 0 1 Contents Indicates program execution point from start address of ROM area Enables conditional branching Stack level 0 Inhibits all interrupts Indicates there is no interrupt request Prevents (masks) interrupt requests
All bits 1 Enables output at level 1 All bits 0 Turns output buffer off (to high impedance) - - 00 All bits 0 - 000 - - 00 0000 Refer to description of port mode register A Refer to description of port mode register B Refer to description of port mode register C
Port mode register C bits (PMRC2, - 000 2, 1, 0 PMRC1, PMRC0) Detection edge select register 1 Detection edge select register 2 Timers/ counters, serial interface Timer mode register A (ESR1) (ESR2) (TMA) 0000 00 - 0000
Disables edge detection Disables edge detection Refer to description of timer mode register A
Timer mode register B1 Timer mode register B2 Timer mode register C1 Timer mode register C2 Timer mode register D1 Timer mode register D2 Serial mode register A Serial mode register B
(TMB1) (TMB2) (TMC1) (TMC2) (TMD1) (TMD2) (SMRA) (SMRB)
0000 - - 00 0000 - 000 0000 0000 0000 - - 00
Refer to description of timer mode register B1 Refer to description of timer mode register B2 Refer to description of timer mode register C1 Refer to description of timer mode register C2 Refer to description of timer mode register D1 Refer to description of timer mode register D2 Refer to description of serial mode register A Refer to description of serial mode register B
15
HD404459 Series
Item Timers/ counters, serial interface Prescaler S Abbr. (PSS) Initial Value $000 Contents --
Prescaler W Timer counter A Timer counter B Timer counter C Timer counter D Timer write register B Timer write register C Timer write register D Octal counter I/O Wakeup set register
(PSW) (TCA) (TCB) (TCC) (TCD) (TWBU, TWBL) (TWCU, TWCL) (TWDU, TWDL)
$00 $00 $00 $00 $00 $X0 $X0 $X0 000
-- -- -- -- -- -- -- -- -- -- -- -- Refer to description of operating modes Refer to description of timer C Refer to description of voltage comparator Refer to description of operating modes Refer to description of timer D Refer to description of timer D Refer to description of operating modes, and oscillator circuit Refer to description of operating modes, and oscillator circuit Switches OSC division ratio
(WSR) (CER) (CCR) (LSON)
0000 0000 0000 0
Voltage Comparator enable comparator register Comparator control register Bit register Low speed on flag Watchdog timer on flag Comparator start flag Direct transfer on flag Input capture status flag Input capture error flag Others Miscellaneous register System clock select register 1 bits 2, 1 System clock select register 2
(WDON) 0 (CMSF) (DTON) (ICSF) (ICEF) (MIS) 0 0 0 0 0000
(SSR12- 00 SSR11) (SSR2) - - 00
Notes: 1. The statuses of other registers and flags after MCU reset are shown in the following table. 2. X indicates invalid value. - indicates that the bit does not exist.
16
HD404459 Series
Status After Status After Cancellation of Stop Status After all Other Cancellation of Stop Mode by STOPC Input Mode by MCU Reset Types of Reset Pre-stop-mode values are not guaranteed; values must be initialized by program Pre-MCU-reset values are not guaranteed; values must be initialized by program
Item Carry flag
Abbr. (CA)
Accumulator B register W register X/SPX register Y/SPY register Serial data register RAM RAM enable flag Port mode register C bit 2
(A) (B) (W) (X/SPX) (Y/SPY) (SRL, SRU) Pre-stop-mode values are retained (RAME) (PMRC) 1 Pre-stop-mode values are retained 0 0 0 0
System clock select (SSR13) register1 bit 3
Table 2
Vector Addresses and Interrupt Priorities
Priority -- 1 2 3 4 5 6 7 Vector Address $0000 $0002 $0004 $0006 $0008 $000A $000C $000E
Reset/Interrupt RESET, STOPC* INT0 INT1 Timer D Timer A, INT2 Timer B, INT3 Timer C, Serial Wakeup
Note: * The STOPC interrupt request is valid only in stop mode.
17
HD404459 Series
$000,0 IE Sequence control * Push PC/CA/ST * Reset IE * Jump to vector address $000,2 INT0 interrupt IF0 $000,3 IM0 $001,0 INT1 interrupt IF1 $001,1 IM1 $001,2 Timer D interrupt IFTD $001,3 IMTD $002,0 Timer A interrupt IFTA $002,1 IMTA $002,2 Timer B interrupt IFTB $002,3 IMTB $003,0 Timer C interrupt IFTC $003,1 IMTC $003,2 Wakeup interrupt IFWU $003,3 IMWU $022,0 IF2 $022,1 IM2 $022,2 IF3 $022,3 IM3 $023,0 IFS $023,1 IMS Serial interrupt INT3 interrupt INT2 interrupt Priority control PLA Vector address
Figure 8 Interrupt Control Circuit
18
HD404459 Series
Table 3 Interrupt Processing and Activation Conditions
Interrupt Source Interrupt Control Bit IE IF0 * IM0 IF1 * IM1 IFTD * IMTD IFTA * IMTA + IF2 * IM2 IFTB * IMTB + IF3 * IM3 IFTC * IMTC + IFS * IMS IFWU * IMWU * * * * * * 1 Note: Bits marked by * can be either 0 or 1. Their values have no effect on operation. * * * * * 1 0 * * * * 1 0 0 INT0 1 1 * * * INT1 1 0 1 * * Timer D 1 0 0 1 * Timer A or Timer B or Timer C or INT3 Serial Wakeup INT2 1 0 0 0 1 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0
Instruction cycles 1 2 3 4 5 6
Instruction execution*
Interrupt acceptance
Stacking IE reset Vector address generation
Execution of JMPL instruction at vector address
Note: * The stack is accessed and the IE reset after the instruction is executed, even if it is a two-cycle instruction.
Execution of instruction at start address of interrupt routine
Figure 9 Interrupt Processing Sequence
19
HD404459 Series
Power on
RESET = 1? Yes
No
Interrupt request? No
Yes
No
IE = 1? Yes
Reset MCU
Execute instruction
Interrupt accept
PC (PC) + 1
IE 0 Stack (PC) Stack (CA) Stack (ST)
PC $0002
Yes
INT0 interrupt? No
PC $0004
Yes
INT1 interrupt? No
PC $0006
Yes
Timer D interrupt? No
PC $0008
Yes
Timer-A/INT2 interrupt? No
PC $000A
Yes
Timer-B/INT 3 interrupt? No
PC $000C
Yes
Timer-C/serial interrupt? No
PC $000E
(wakeup interrupt)
Figure 10 Interrupt Processing Flowchart
20
HD404459 Series
Interrupt Enable Flag (IE: $000, Bit 0): Controls the entire interrupt process. It is reset by the interrupt processing and set by the RTNI instruction. Refer to table 4. Table 4
IE 0 1
Interrupt Enable Flag (IE: $000, Bit 0)
Interrupt Enabled/Disabled Disabled Enabled
External Interrupts (INT0 , INT1, INT2, INT3, WU0-WU7): Five external interrupt signals. External Interrupt Request Flags (IF0, IF1, IF2, IF3, IFWU: $000, $001, $003, $022): IF0, IF1, and IFWU are set at the falling edge of input signals, and IF2 and IF3 are set at the rising or falling edge or both rising and falling edges of input signals (table 5). INT2 and INT3 interrupt edges are selected by the detection edge select register (ESR1: $026) (figure 11). Table 5 External Interrupt Request Flags (IF0-IF3, IFWU: $000, $001, $003, $022)
Interrupt Request No Yes
IF0-IF3, IFWU 0 1
Detection edge selection register 1 (ESR1: $026) Bit Initial value Read/Write Bit name 3 0 W ESR13 2 0 W ESR12 1 0 W ESR11 0 0 W ESR10
ESR13 0
ESR12 0 1
INT3 detection edge No detection Falling-edge detection Rising-edge detection Double-edge detection*
ESR11 0
ESR10 0 1
INT2 detection edge No detection Falling-edge detection Rising-edge detection Double-edge detection*
1
0 1
1
0 1
Note: * Both falling and rising edges are detected.
Figure 11 Detection Edge Selection Register 1 (ESR1)
21
HD404459 Series
External Interrupt Masks (IM0, IM1, IM2, IM3, IMWU: $000, $001, $003, $022): Prevent (mask) interrupt requests caused by the corresponding external interrupt request flags (table 6). Table 6 External Interrupt Masks (IM0-1M3, IMWU: $000, $001, $003, $022)
Interrupt Request Enabled Disabled (masked)
IM0-IM3, IMWU 0 1
Timer A Interrupt Request Flag (IFTA: $002, Bit 0): Set by overflow output from timer A (table 7). Table 7
IFTA 0 1
Timer A Interrupt Request Flag (IFTA: $002, Bit 0)
Interrupt Request No Yes
Timer A Interrupt Mask (IMTA: $002, Bit 1): Prevents (masks) an interrupt request caused by the timer A interrupt request flag (table 8). Table 8
IMTA 0 1
Timer A Interrupt Mask (IMTA: $002, Bit 1)
Interrupt Request Enabled Disabled (masked)
Timer B Interrupt Request Flag (IFTB: $002, Bit 2): Set by overflow output from timer B (table 9). Table 9
IFTB 0 1
Timer B Interrupt Request Flag (IFTB: $002, Bit 2)
Interrupt Request No Yes
Timer B Interrupt Mask (IMTB: $002, Bit 3): Prevents (masks) an interrupt request caused by the timer B interrupt request flag (table 10). Table 10
IMTB 0 1
Timer B Interrupt Mask (IMTB: $002, Bit 3)
Interrupt Request Enabled Disabled (masked)
22
HD404459 Series
Timer C Interrupt Request Flag (IFTC: $003, Bit 0): Set by overflow output from timer C (table 11). Table 11
IFTC 0 1
Timer C Interrupt Request Flag (IFTC: $003, Bit 0)
Interrupt Request No Yes
Timer C Interrupt Mask (IMTC: $003, Bit 1): Prevents (masks) an interrupt request caused by the timer C interrupt request flag (table 12). Table 12
IMTC 0 1
Timer C Interrupt Mask (IMTC: $003, Bit 1)
Interrupt Request Enabled Disabled (masked)
Timer D Interrupt Request Flag (IFTD: $001, Bit 2): Set by overflow output from timer D, or by the rising or falling edge of signals input to EVND when the input capture function is used (table 13). Table 13
IFTD 0 1
Timer D Interrupt Request Flag (IFTD: $001, Bit 2)
Interrupt Request No Yes
Timer D Interrupt Mask (IMTD: $001, Bit 3): Prevents (masks) an interrupt request caused by the timer D interrupt request flag (table 14). Table 14
IMTD 0 1
Timer D Interrupt Mask (IMTD: $001, Bit 3)
Interrupt Request Enabled Disabled (masked)
23
HD404459 Series
Serial Interrupt Request Flags (IFS: $023, Bit 0): Set when data transfer is completed or when data transfer is suspended (table 15). Table 15
IFS 0 1
Serial Interrupt Request Flag (IFS: $023, Bit 0)
Interrupt Request No Yes
Serial Interrupt Mask (IMS: $023, Bit 1): Prevents (masks) an interrupt request caused by the serial interrupt request flag (table 16). Table 16
IMS 0 1
Serial Interrupt Mask (IMS: $023, Bit 1)
Interrupt Request Enabled Disabled (masked)
Wakeup Interrupt Request Flag (IFWU: $003, Bit 2): Set by the falling edge of signals input to wakeup (table 17). Table 17
IFWU 0 1
Wakeup Interrupt Request Flag (IFWU: $003, Bit 2)
Interrupt Request No Yes
Wakeup Interrupt Mask (IMWU: $003, Bit 3): Prevents (masks) an interrupt request caused by the wakeup interrupt request flag (table 18). Table 18
IMWU 0 1
Wakeup Interrupt Mask (IMWU: $003, Bit 3)
Interrupt Request Enabled Disabled (masked)
24
HD404459 Series
Wakeup Function: Detects the falling edge of wakeup input signals and sets the wakeup interrupt request flag (IFWU: $003, bit 2). Refer to figure 12 for a block diagram showing the wakeup interrupt. The wakeup select register (WSR: $018) can select from one to eight wakeup inputs (WU0-WU 7) (figure 13). The wakeup function can operate in any mode other than stop mode. When the wakeup interrupt is received, the CPU generates an independent vector address ($000E). Note: The wakeup select register (WSR: $018) controls whether the wakeup input is to be valid or invalid, but it can not switch the pin inputs between the R ports and wakeup. When using the pins only as R ports, nullify wakeup input or set the wakeup interrupt mask (IMWU: $003, bit 3).
R50/WU0 R51/WU1 R52/WU2 R53/WU3 R60/WU4 R61/WU5 R62/WU6 R63/WU7 Falling-edge detection Wakeup interrupt request flag
4 WSR (4 bits) Wakeup selection register
4 Internal bus
Figure 12 Wakeup Interrupt
25
HD404459 Series
Bit Initial value Read/Write Bit name 3 0 W WSR3 2 0 W WSR2 1 0 W WSR1 0 0 W WSR0
WSR0 0 1
WU0 to WU3 control Invalid Valid
WSR1 0 1
WU4 to WU5 control Invalid Valid
WSR2 0 1
WU6 control Invalid Valid
WSR3 0 1
WU7 control Invalid Valid
Figure 13 Wakeup Select Register (WSR)
26
HD404459 Series
Operating Modes
The MCU has five operating modes (table 19). Refer to tables 20 and 21 for the operations in each mode, and figure 14 for the transitions between operating modes. Active Mode: All MCU functions operate according to the clock generated by the system oscillators OSC1 and OSC2. Table 19 Operating Modes and Clock Status
Mode Name Active Standby Stop Watch Subactive*2 INT0, timer A or wakeup interrupt request from watch mode
SBY instruction STOP STOP Activation method RESET instruction when instruction when cancellation, TMA3 = 0 TMA3 = 1 interrupt request, STOPC cancellation in stop mode, STOP/SBY instruction in subactive mode (when direct transfer is selected) Status System oscillator OP OP OP Stopped OP*1 Stopped OP
Stopped OP
Subsystem OP oscillator Cancellation method RESET input, STOP/SBY instruction
RESET input, RESET input, RESET input, RESET input, interrupt request STOPC input in INT0, timer A or STOP/SBY stop mode wakeup interrupt instruction request
Note: OP implies in operation 1. Operating or stopping the oscillator can be selected by setting bit 3 of the system clock select register (SSR1 : $029). 2. Subactive mode is an optional function; specify it on the function option list.
27
HD404459 Series
Table 20
Function CPU RAM Timer A Timer B Timer C Timer D SCI Comparator I/O
Operations in Low-Power Dissipation Modes
Stop Mode Reset Retained Reset Reset Reset Reset Reset Reset Reset*
1
Watch Mode Retained Retained OP Stopped Stopped Stopped Stopped* Stopped Retained
3
Standby Mode Retained Retained OP OP OP OP OP OP Retained
Subactive Mode*2 OP OP OP OP OP OP OP Stopped OP
Note: OP implies in operation 1. Output pins are at high impedance. 2. Subactive mode is an optional function to be specified on the function option list. 3. Transmission/reception is activated if a clock is input in external clock mode. However, all interrupts stop.
Table 21
I/O Status in Low-Power Dissipation Modes
Output Standby Mode, Watch Mode Stop Mode High impedance -- High impedance Input Active Mode, Subactive Mode Input enabled Input enabled Input enabled
D0-D 9 D10-D 11 R0-R8 R9 0, R9 1, R9 2 R9 3, RA
Retained -- Retained or output of peripheral functions --
--
Input enabled
28
HD404459 Series
Reset by RESET input or by watchdog timer Stop mode
(TMA3 = 0, SSR13 = 0)
RAME = 0 RESET1
RAME = 1 RESET2
STOPC
fOSC: fX: o CPU: o CLK: o PER:
Stop Oscillate Stop Stop Stop
PC O ST
Standby mode fOSC: fX: o CPU: o CLK: o PER: Oscillate Oscillate Stop fcyc fcyc SBY Interrupt
Active mode fOSC: fX: o CPU: o CLK: o PER: Oscillate Oscillate fcyc fcyc fcyc
(TMA3 = 0)
ST
O
P
(TMA3 = 0, SSR13 = 1)
STOP
fOSC: fX: o CPU: o CLK: o PER:
Stop Stop Stop Stop Stop
Watch mode
(TMA3 = 1) (TMA3 = 1, LSON = 0)
fOSC: fX: o CPU: o CLK: o PER:
Oscillate Oscillate Stop fW fcyc
SBY Interrupt
fOSC: fX: o CPU: o CLK: o PER: Subactive mode fOSC: fX: o CPU: o CLK: o PER:
Oscillate Oscillate fcyc fW fcyc
*2 *3
STOP INT0, WU0 to WU7, timer A*1
ST
*4
fOSC: fX: o CPU: o CLK: o PER:
Stop Oscillate Stop fW Stop
Main oscillation frequency Suboscillation frequency for time-base fOSC/4, fOSC/8, fOSC/16, fcyc: fOSC/32 (software selectable) fW: fX/8 fX/8 or fX/4 fSUB: (software selectable) o CPU: System clock o CLK: Clock for time-base o PER: Clock for other peripheral functions LSON: Low speed on flag DTON: Direct transfer on flag fOSC: fX:
OP
(TMA3 = 1, LSON = 1)
Stop Oscillate fSUB fW fSUB
INT0, WU0 to WU7 , timer A*1
fOSC: fX: o CPU: o CLK: o PER:
Stop Oscillate Stop fW Stop
Notes: 1. 2. 3. 4.
Interrupt source STOP/SBY (DTON = 1, LSON = 0) STOP/SBY (DTON = 0, LSON = 0) STOP/SBY (DTON = Don't care, LSON = 1)
Figure 14 MCU Status Transitions
29
HD404459 Series
Standby Mode: In standby mode, the oscillators continue to operate, but the clocks related to instruction execution stop. Therefore, the CPU operation stops, but all RAM and register contents are retained, and the D or R port status, when set to output, is maintained. Peripheral functions such as interrupts, timers, and serial interface continue to operate. The power dissipation in this mode is lower than in active mode since the CPU halts. The MCU enters standby mode when the SBY instruction is executed in active mode. Standby mode is terminated by RESET input or an interrupt request. If it is terminated by RESET, the MCU is reset as well. After an interrupt request, the MCU enters active mode and executes the next instruction after the SBY instruction. If the interrupt enable flag is 1, the interrupt is then processed; if it is 0, the interrupt request is left pending and normal instruction execution continues. See figure 15 for the flowchart of operation in standby mode.
Stop Oscillator: Stop Suboscillator: Active/Stop Peripheral clocks: Stop All other clocks: Stop Standby Watch
Oscillator: Active Peripheral clocks: Active All other clocks: Stop
Oscillator: Stop Suboscillator: Active Peripheral clocks: Stop All other clocks: Stop
No
RESET = 1?
RESET = 1?
No
Yes No
STOPC = 0?
Yes
IF0 * IM0 = 1?
No
Yes Yes
IF1 * IM1 = 1?
No
Yes
IFTD * IMTD = 1?
No
IFTA * IMTA + IF2 * IM2 = 1?
Yes
No
IFTB * IMTB + IF3 * IM3 = 1?
RAME = 1
RAME = 0
Yes*
No
IFTC * IMTC + IFS * IMS = 1?
Yes
No
Yes
IFWU * IMWU = 1?
No
(SBY only)
(SBY only)
(SBY only)
(SBY only)
Yes
Restart processor clocks
Execute next instruction
Restart processor clocks
No
IF = 1, IM = 0, and IE = 1?
Yes
Reset MCU
Execute next instruction
Accept interrupt
Note: * The INT2 interrupt is valid only by standby mode cancellation.
Figure 15 MCU Operation Flowchart
30
,
HD404459 Series
Stop Mode: In stop mode, all MCU operations stop and RAM data is retained. Therefore, the power dissipation in this mode is the least of all modes. The OSC1 and OSC 2 oscillator stops. Operation of the X1 and X2 oscillator can be selected by setting bit 3 of the system clock select register (SSR1: $029; operating: SSR13 = 0, stop: SSR13 = 1) (figure 24). The MCU enters stop mode if the STOP instruction is executed in active mode when bit 3 of timer mode register A (TMA: $008) is set to 0 (TMA3 = 0) (figure 40). Stop mode is terminated by RESET input or STOPC input (figure 16). RESET or STOPC must be applied for at least one tRC to stabilize oscillation (refer to the AC Characteristics section). When the MCU restarts after stop mode is cancelled, all RAM contents before entering stop mode are retained, but the accuracy of the contents of the accumulator, B register, W register, X/SPX register, Y/SPY register, carry flag, and serial data register cannot be guaranteed.
Stop mode Oscillator Internal clock RESET STOPC tres STOP instruction execution tres tRC (stabilization period)
Figure 16 Timing of Stop Mode Cancellation
Watch Mode: In watch mode, the clock function (timer A) using the X1 and X2 oscillator operate but other function operations stop. Therefore, the power dissipation in this mode is the second least to stop mode, and is also convenient when only clock display is used. In this mode, the OSC1 and OSC 2 oscillator stops, but the X1 and X2 oscillator operates. The MCU enters watch mode if the STOP instruction is executed in active mode when TMA3 = 1, or if the STOP or SBY instruction is executed in subactive mode.
Watch mode is terminated by a RESET input, timer A interrupt request, INT0 interrupt request, or wakeup interrupt request. For details of RESET input, refer to the Stop Mode section. When terminated by a timer A interrupt request, an INT0 nterrupt request, or wakeup interrupt request, the MCU enters active mode if LSON is 0 or subactive mode if LSON is 1. After an interrupt request is generated, the time required to enter active mode is tRC for a timer A interrupt, and TX (where T + tRC < TX < 2T + tRC ) for an INT0 interrupt, as shown in figure 17. Operation during mode transition is the same as that at standby mode cancellation (figure 15).
31
HD404459 Series
Oscillation stabilization period Active mode Watch mode Active mode
Inte, rupt, trobe Interrupt strobe INT0 , WU0 - WU 7 Interrupt request generation
(During the transition from watch mode to active mode only) Interrupt frame length T: t RC : Oscillation stabilization period
T
T Tx
t RC
T + t RC < Tx < 2T + t RC
Figure 17 Interrupt Frame Subactive Mode: The OSC1 and OSC2 oscillator stops and the MCU operates with a clock generated by the X1 and X2 oscillator. In this mode, functions other than the voltage comparator operate. However, because the operating clock is slow, the power dissipation becomes low, next to watch mode. The CPU instruction execution speed can be selected as 244 s or 122 s by setting bit 2 (SSR12) of the system clock select register (SSR1: $029). Note that the SSR12 value must be changed in active mode. If the value is changed in subactive mode, the MCU may malfunction. When the STOP or SBY instruction is executed in subactive mode, the MCU enters either watch or active mode, depending on the statuses of the low speed on flag (LSON: $020, bit 0) and the direct transfer on flag (DTON: $020, bit 3). Subactive mode is an optional function that the user must specify on the function option list. Interrupt Frame: In watch and subactive modes, o CLK is applied to timer A and the INT0 and WU0-WU 7 circuits. Prescaler W and timer A operate as the time-base and generate the timing clock for the interrupt frame. Three interrupt frame lengths (T) can be selected by setting the miscellaneous register (MIS: $00C) (figure 18). In watch and subactive modes, a timer A/ INT0 wakeup interrupt is generated synchronously with the interrupt frame. The interrupt request is generated synchronously with the interrupt strobe timing except during transition to active mode. The falling edge of the INT0 and WU0-WU7 signals is input asynchronously with the interrupt frame timing, but it is regarded as input synchronously with the second interrupt strobe clock after the falling edge. An overflow and interrupt request in timer A is generated synchronously with the interrupt strobe timing.
32
HD404459 Series
Miscellaneous register (MIS: $00C) Bit Initial value Read/Write Bit name 3 0 W MIS3 2 0 W MIS2 1 0 W MIS1 0 0 W MIS0
MIS3
MIS2
MIS1 0
MIS0 0
T *1
tRC *1
Oscillation circuit conditions External clock input
Buffer control. Refer to figure 39.
0.24414 ms 0.12207 ms 0.24414 ms*2
1 1 0 1
15.625 ms 125 ms Not used
7.8125 ms 62.5 ms Ceramic or crystal oscillator --
Notes: 1. The values of T and tRC are applied when a 32.768-kHz crystal oscillator is used. 2. The value is applied only when direct transfer operation is used.
Figure 18 Miscellaneous Register (MIS) Direct Transition from Subactive Mode to Active Mode: Available by controlling the direct transfer on flag (DTON: $020, bit 3) and the low speed on flag (LSON: $020, bit 0). The procedures are described below: 1. Set LSON to 0 and DTON to 1 in subactive mode. 2. Execute the STOP or SBY instruction. 3. The MCU automatically enters active mode from subactive mode after waiting for the MCU internal processing time and oscillation stabilization time (figure 19). Notes: The DTON flag ($020, bit 3) can be set only in subactive mode. It is always reset in active mode. The transition time (TD) from subactive mode to active mode is: tRC < TD < T + tRC
33
HD404459 Series
STOP/SBY instruction execution Subactive mode (Set LSON = 0, DTON = 1) Interrupt strobe Direct transfer completion timing T Interrupt frame length T: t RC : Oscillation stabilization period t RC MCU internal processing period Oscillation stabilization time
Active mode
Figure 19 Direct Transition Timing Stop Mode Cancellation by STOPC : The MCU enters active mode from stop mode by a STOPC input as well as by RESET. In either case, the MCU starts instruction execution from the starting address (address 0) of the program. However, the value of the RAM enable flag (RAME: $021, bit 3) differs between cancellation by STOPC and by RESET. When stop mode is cancelled by RESET, RAME = 0; when cancelled by STOPC, RAME = 1. RESET can cancel all modes, but STOPC is valid only in stop mode; STOPC input is ignored in other modes. Therefore, when the program requires to confirm that stop mode has been cancelled by STOPC (i.e., when the RAM contents before entering stop mode are used after transition to active mode), execute the TEST instruction on the RAM enable flag (RAME) at the beginning of the program. MCU Operation Sequence: See figures 20 to 22 for the MCU operation sequences. It is reset by an asynchronous RESET input, regardless of its status. The low-power mode operation sequence is shown in figure 22. With the IE flag cleared and an interrupt flag set together with its interrupt mask cleared, if a STOP/SBY instruction is executed, the instruction is cancelled (regarded as an NOP) and the following instruction is executed. Before executing a STOP/SBY instruction, make sure all interrupt flags are cleared or all interrupts are masked.
34
HD404459 Series
Power on
RESET = 1? Yes
No
RAME = 0
MCU operation cycle
Reset MCU
Figure 20 MCU Operating Sequence (Power On)
35
HD404459 Series
MCU operation cycle
IF = 1?
Yes
No
No
IM = 0 and IE = 1?
Yes Instruction execution
Yes
SBY, STOP instruction?
IE 0 Stack (PC), (CA), (ST)
No
Low-power mode operation cycle
PC Next location
PC Vector address
IF: IM: IE: PC: CA: ST:
Interrupt request flag Interrupt mask Interrupt enable flag Program counter Carry flag Status flag
Figure 21 MCU Operating Sequence (MCU Operation Cycle)
36
HD404459 Series
Low-power mode operation cycle
IF = 1 and IM = 0? *
No
Yes
Standby/Watch mode
Stop mode
No
IF = 1 and IM = 0?
No
STOPC = 0?
Yes Hardware NOP execution Hardware NOP execution
Yes
RAME = 1
PC Next Iocation
PC Next Iocation
Reset MCU
Instruction execution
MCU operation cycle
Note: * For IF and IM operation, refer to figure 15.
Figure 22 MCU Operating Sequence (Low-Power Mode Operation)
37
HD404459 Series
Notes on Use: * When the MCU is in watch mode or subactive mode, if the high level period before the falling edge of INT 0 and WU0-WU 7 is shorter than the interrupt frame, INT 0 and WU0-WU 7 will not be detected. Also, if the low level period after the falling edge of INT0 and WU0-WU 7 is shorter than the interrupt frame, INT0 and WU0-WU 7 will not be detected. Edge detection is shown in figure 23. The level of the INT 0 and WU0-WU 7 signals are sampled by a sampling clock. When this sampled value changes from high to low, a falling edge is detected. In figure 24, the level of the INT0 and WU0-WU 7 signals are sampled by an interrupt frame. In (a) the sampled value is low at point A, and also low at point B. Therefore, a falling edge will not be detected. In (b), the sampled value is high at point A, and also high at point B. A falling edge will not be detected in this case either. When the MCU is in watch mode or subactive mode, keep the high level and low level periods of INT 0 and WU 0-WU 7 longer than interrupt frame.
INT0, WU0-WU7
Sampling High Low Low
Figure 23 Edge Detection
INT0, WU0-WU7
INT0, WU0-WU7
Interrupt frame
A: Low
B: Low
Interrupt frame
A: High
B: High
a. High level period
b. Low level period
Figure 24 Sampling Example
38
HD404459 Series
Internal Oscillator Circuit
Clock Generation Circuit See figure 25 for a block diagram of the clock generation circuit. A ceramic oscillator or crystal oscillator can be connected to OSC1 and OSC2, and a 32.768-kHz oscillator can be connected to X1 and X2 (table 22). The system oscillator can also be operated by an external clock. Bit 1 (SSR11) of system clock select register 1 (SSR1: $029) must be selected according to the frequency of the oscillator connected to OSC1 and OSC2(figure 26). Note: If the system clock select register 1 (SSR1: $029) setting does not match the oscillator frequency, subsystems using the 32.768-kHz oscillation will malfunction.
LSON
OSC2 OSC1
1/4, 1/8, System fOSC 1/16, or oscillator 1/32 division circuit*1
fcyc tcyc
Timing generator circuit
oCPU System clock selection circuit oPER
CPU with ROM, RAM, registers, flags, and I/O
Peripheral function interrupt
fX
fSUB Timing 1/8 or 1/4 tsubcyc generator division circuit circuit*2
X1 X2
Subsystem oscillator
TMA3
1/8 division circuit
fW tWcyc
Timing generator circuit
Time-base clock o CLK selection circuit
Time-base interrupt
Notes: 1. 1/4, 1/8, 1/16, or 1/32 division ratio can be selected by setting bits 0 and 1 of system clock select register 2 (SSR2). 2. 1/8 or 1/4 division ratio can be selected by setting bit 2 of system clock select register 1 (SSR1).
Figure 25 Clock Generation Circuit
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HD404459 Series
Selection of Division Ratio Division Ratio of the System Clock: 1/4, 1/8, 1/16, or 1/32 division ratio of the system clock can be selected by setting bits 0 and 1 (SSR20 and SSR21) of system clock select register 2 (SSR2: $02A). The values of SSR20 and SSR21 become valid when entering the watch mode after making the ratio selection. (However, the value of SSR2 becomes valid immediately after the selection.) Therefore, when changing the division ratio, the system clock must be stopped. There are two methods for selecting the division ratio of the system clock as follows. * Division ratio is selected by writing to SSR20 and SSR21 in active mode. The selected values of SSR20 and SSR21 are valid before the MCU enters watch mode. The division ratio of the system clock becomes the written value when the MCU returns to the active mode from the watch mode. * Division ratio is selected by writing to SSR20 and SSR21 in subactive mode. The division ratio of the system clock becomes the selected value when the MCU returns to active mode after entering watch mode. Note: SSR2 is cleared in the reset and stop modes. Therefore, 1/4 division ratio of the system clock is selected when the MCU returns from stop mode after reset. Division Ratio of the Subsystem Clock: 1/4 or 1/8 division ratio of the subsystem clock can be selected by setting bit 2 (SSR12) of system clock select register 1 (SSR1: $029). The value of SSR12 becomes valid immediately after the ratio selection. When the value of SSR12 is changed, the MCU must be in active mode. If the value of SSR12 is changed in subactive mode, the MCU may malfunction.
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HD404459 Series
System clock select register 1 (SSR1: $029) Bit Initial value Read/Write Bit name 3 0 W SSR13* 2 0 W SSR12 1 0 W 0 -- --
SSR11 Not used
SSR11 0 1 SSR12 0 1 SSR13 0 1
System oscillation frequency selection 1.6 to 4.0 MHz 0.4 to 1.0 MHz 32-kHz oscillation division ratio selection fsub = fx/8 fsub = fx/4 32-kHz oscillation stop Oscillation operates in stop mode Oscillation stops in stop mode
Note: * SSR13 is reset to 0 only by RESET input. When STOPC is input in stop mode, SSR13 is not reset but retains its value. SSR13 is not reset in stop mode.
Figure 26 System Clock Select Register 1 (SSR1: $029)
System clock select register 2 (SSR2: $02A) Bit Initial value Read/Write Bit name 3 -- -- 2 -- -- 1 0 W 0 0 W SSR20
Not used Not used SSR21
SSR21 0
SSR20 0 1
System clock division ratio selection 1/4 1/8 1/16 1/32
1
0 1
Figure 27 System Clock Select Register 2 (SSR2: $02A)
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HD404459 Series
RESET
X1
X2
GND
OSC2 OSC1 TEST GND
Figure 28 Typical Layout of Crystal and Ceramic Oscillators
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HD404459 Series
Table 22 Oscillator Circuit Examples
Circuit Configuration External clock operation
External oscillator OSC 1
Circuit Constants
Open
OSC 2
Ceramic oscillator (OSC1, OSC 2)
C1 OSC1 Ceramic Rf OSC2 C2 GND
Ceramic oscillator: CSA4.00MG (Murata) Rf = 1 M 20% C1 = C2 = 30 pF
Crystal oscillator (OSC1, OSC 2)
C1 OSC1 Crystal Rf OSC2 C2 GND L OSC1 C0 CS RS OSC2
Rf = 1 M 20% C1 = C2 = 10-22 pF 20% Crystal: Equivalent to circuit shown below C0: 7 pF max. RS: 100 max.
Crystal oscillator (X1, X2)
C1 X1 Crystal X2 C2 GND L X1 C0 CS RS X2
Crystal: 32.768 kHz: MX38T (Nippon Denpa Kogyo) C1 = C2 = 15 pF 5% RS: 14 k C0: 1.5 pF
Notes: 1. Since the circuit constants change depending on the crystal or ceramic resonator and stray capacitance of the board, the user should consult with the crystal or ceramic oscillator manufacturer to determine the circuit parameters. 2. Wiring among OSC1, OSC 2, X1, X2, and elements should be as short as possible, and must not cross other wiring (figure 28). 3. If the 32.768-kHz crystal oscillator is not used, the X1 pin must be fixed to GND and X2 must be open.
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HD404459 Series
Input/Output
The MCU has 49 input/output pins (D0-D9, R0-R8, R90-R92) and 7 input pins (D 10, D11, R93, RA). The features are described as follows. * The D11, R0, R3-R6, R93, and RA pins are multiplexed with peripheral function pins such as those for timers or the serial interface. See table 24. For these pins, the peripheral function setting is done prior to the D or R port setting. Therefore, when a peripheral function is selected for a pin, the pin function and input/output selection are automatically switched according to the setting. However, pins input to the wakeup function are not switched. Only the valid/invalid statuses of wakeup input are controlled. * Peripheral function output pins are CMOS out-put pins. See table 23. Only the SO pin and R4 3 port can be set to NMOS open-drain output by software. * In stop mode, the MCU is reset, and therefore peripheral function selection is cancelled. Input/output pins are set at high-impedance. * Each input/output pin has a built-in pull-up MOS (figure 29), which can be individually turned on or off by software.
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HD404459 Series
Table 23 Programmable I/O Circuits
0 0 0 PMOS NMOS Pull-up MOS Note: -- indicates off status. -- -- -- 1 -- -- -- 1 0 -- On -- 1 On -- -- 1 0 0 -- -- -- 1 -- -- On 1 0 -- On -- 1 On -- On
MIS3 (Bit 3 of MIS) DCD, DCR PDR CMOS buffer
HLT VCC Pull-up MOS VCC Pull-up control signal MIS3
Buffer control signal DCD, DCR
Output data
PDR
Input data Input control signal
Figure 29 I/O Buffer Configuration
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HD404459 Series
Table 24
I/O Pin Type Input/output pins
Circuit Configurations of I/O Pins
Circuit
VCC HLT VCC Pull-up control signal Buffer control signal Output data Input data Input control signal VCC HLT VCC Pull-up control signal Buffer control signal MIS3 DCR MIS2 PDR MIS3 DCD, DCR PDR
Pins D0-D 9, R0 0-R0 3, R1 0-R1 3, R20-R2 3, R3 0-R3 3, R40-R4 2, R5 0-R5 3, R60-R6 3, R7 0-R7 3, R80-R8 3, R9 0-R9 2
R4 3
Output data Input data Input control signal
Input pins
Input data Input control signal
D10, D11, R9 3, RA0-RA 3
HLT
Peripheral function pins
Input/ output pins
VCC
SCK
VCC
Pull-up control signal
MIS3
Output data Input data SCK
SCK
Output pins
VCC
HLT VCC Pull-up control signal MIS3
SO
PMOS control signal Output data HLT VCC Pull-up control signal MIS3
MIS2 SO
VCC
TOB, TOC, TOD
Output data
TOB, TOC, TOD
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HD404459 Series
I/O Pin Type Peripheral function pins Input pins Circuit
VCC HLT MIS3 PDR INT0, etc Input data STOPC
Pins SI, INT0, INT1, INT2, INT3, WU0-WU7, EVNB, EVND STOPC
Notes: 1. In stop mode, the MCU is reset and peripheral function selection is cancelled. The HLT signal becomes low, and input/output pins enter high-impedance state. 2. The HLT signal is 1 in watch and subactive modes.
D Port (D0-D 11): Consist of 10 input/output pins and 2 input pins addressed by one bit. D 0-D 9 are input/output pins, and D10 and D11 are input-only pins. Pins D0-D 9 are set by the SED and SEDD instructions, and reset by the RED and REDD instructions. Output data is stored in the port data register (PDR) for each pin. All pins D0-D11 are tested by the TD and TDD instructions. The on/off statuses of the output buffers are controlled by D-port data control registers (DCD0-DCD2: $02C-$02E) that are mapped to memory addresses (figure 30). Pin D11 is multiplexed with peripheral function pin STOPC. The peripheral function mode of this pin is selected by bit 2 (PMRC2) of port mode register C (PMRC: $025) (figure 35).
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HD404459 Series
R Ports (R0-RA): 39 input/output pins and 5 input pins addressed in 4-bit units. Data is input to these ports by the LAR and LBR instructions, and output from them by the LRA and LRB instructions. Output data is stored in the port data register (PDR) for each pin. The on/off statuses of the output buffers of the R ports are controlled by R-port data control registers (DCR0-DCR9: $030-$039) that are mapped to memory addresses (figure 30).
Data control register DCD0, DCD1 Bit Initial value Read/Write Bit name DCD2 Bit Initial value Read/Write Bit name (DCD0 to DCD2: $02C to $02E) (DCR0 to DCR9: $030 to $039) 2 0 W 1 0 W 0 0 W
3 0 W
DCD03, DCD02, DCD01, DCD00, DCD13 DCD12 DCD11 DCD10 3 -- -- 2 -- -- 1 0 W 0 0 W DCD20
Not used Not used DCD21
DCR0 to DCR8 Bit Initial value Read/Write Bit name DCR9 Bit Initial value Read/Write Bit name All Bits 0 1
3 0 W
2 0 W
1 0 W
0 0 W
DCR03- DCR02- DCR01- DCR00- DCR83 DCR82 DCR81 DCR80 3 -- -- 2 0 W 1 0 W DCR91 0 0 W DCR90
Not used DCR92
CMOS Buffer On/Off Selection Off (high-impedance) On
Correspondence between ports and DCD/DCR bits Register Name DCD0 DCD1 DCD2 DCR0 DCR1 DCR2 DCR3 DCR4 DCR5 DCR6 DCR7 DCR8 DCR9 Bit 3 D3 D7 -- R03 R13 R23 R33 R43 R53 R63 R73 R83 -- Bit 2 D2 D6 -- R02 R12 R22 R32 R42 R52 R62 R72 R82 R92 Bit 1 D1 D5 D9 R01 R11 R21 R31 R41 R51 R61 R71 R81 R91 Bit 0 D0 D4 D8 R00 R10 R20 R30 R40 R50 R60 R70 R80 R90
Figure 30 Data Control Registers (DCD, DCR)
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HD404459 Series
Pins R00-R03 are multiplexed with peripheral pins INT0-INT 3, respectively. The peripheral function modes of these pins are selected by bits 0-3 (PMRB0-PMRB3) of port mode register B (PMRB: $024) (figure 31).
Port mode register B (PMRB: $024) Bit Initial value Read/Write Bit name 3 0 W PMRB3 2 0 W 1 0 W 0 0 W
PMRB2 PMRB1 PMRB0
PMRB0 0 1 PMRB1 0 1 PMRB2 0 1 PMRB3 0 1
R00/INT0 mode selection R00 INT0 R01/INT1 mode selection R01 INT1 R02/INT2 mode selection R02 INT2 R03 /INT3 mode selection R03 INT3
Figure 31 Port Mode Register B (PMRB)
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HD404459 Series
Pins R30-R32 are multiplexed with peripheral pins TOB, TOC, and TOD, respectively. The peripheral function modes of these pins are selected by bits 0 and 1 (TMB20, TMB21) of timer mode register B2 (TMB2: $013), bits 0-2 (TMC20-TMC22) of timer mode register C2 (TMC2: $014), and bits 0-3 (TMD20-TMD23) of timer mode register D2 (TMD2: $015) (figures 32, 33, and 34).
Timer mode register B2 (TMB2: $013) Bit Initial value Read/Write Bit name 3 -- -- 2 -- -- 1 0 R/W 0 0 R/W TMB20
Not used Not used TMB21
TMB21 0
TMB20 0 1
R30/TOB mode selection R30 TOB TOB TOB R30 port Toggle output 0 output 1 output
1
0 1
Figure 32 Timer Mode Register B2 (TMB2)
Timer mode register C2 (TMC2: $014) Bit Initial value Read/Write Bit name 3 -- -- Not used 2 0 R/W TMC22 1 0 R/W TMC21 0 0 R/W TMC20
TMC22 0
TMC21 0
TMC20 0 1
R31/TOC mode selection R31 TOC TOC TOC TOC TOC TOC TOC R31 port Toggle output 0 output 1 output Not used Not used Not used PWM output
1
0 1
1
0
0 1
1
0 1
Figure 33 Timer Mode Register C2 (TMC2)
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HD404459 Series
Timer mode register D2 (TMD2: $015) Bit Initial value Read/Write Bit name 3 0 R/W TMD23 2 0 R/W TMD22 1 0 R/W TMD21 0 0 R/W TMD20
TMD23 0
TMD22 0
TMD21 0
TMD20 0 1 R32
R32/TOD mode selection R32 port Toggle output 0 output 1 output Not used Not used Not used PWM output Input capture (R32 port)
TOD TOD TOD TOD TOD TOD TOD R32
1
0 1
1
0
0 1
1
0 1
1
Don't care Don't care Don't care
Figure 34 Timer Mode Register D2 (TMD2)
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HD404459 Series
Pins R33 and R40 are multiplexed with peripheral pins EVNB and EVND, respectively. The peripheral function modes of these pins are selected by bits 0 and 1 (PMRC0, PMRC1) of port mode register C (PMRC: $025) (figure 35).
Port mode register C (PMRC: $025) Bit Initial value Read/Write Bit name 3 -- -- 2 0 W 1 0 W 0 0 W PMRC0
Not used PMRC2* PMRC1
PMRC0 0 1 PMRC1 0 1 PMRC2 0 1
R33/EVNB mode selection R33 EVNB R40/EVND mode selection R40 EVND D11/STOPC mode selection D11 STOPC
Note: * PMRC2 is reset to 0 only by RESET input. When STOPC is input in stop mode, PMRC2 is not reset but retains its value.
Figure 35 Port Mode Register C (PMRC)
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HD404459 Series
Pins R41-R4 3 are multiplexed with peripheral pins SCK, SI, and SO, respectively. The peripheral function modes of these pins are selected by bit 3 (SMRA3) of serial mode register A (SMRA: $005), and bits 0 and 1 (PMRA0, PMRA1) port mode register A (PMRA: $004) (figures 36 and 37).
Port mode register A (PMRA: $004) Bit Initial value Read/Write Bit name 3 -- -- 2 -- -- 1 0 W 0 0 W
Not used Not used PMRA1 PMRA0
PMRA0 0 1 PMRA1 0 1
R43/SO mode selection R43 SO R42/SI mode selection R42 SI
Figure 36 Port Mode Register A (PMRA)
Serial mode register A (SMRA: $005)
Bit Initial value Read/Write Bit name
3 0 W SMRA3
2 0 W
1 0 W
0 0 W
SMRA2 SMRA1 SMRA0
SMRA3 0 1
R41/SCK mode selection R41 port SCK
SMRA2
SMRA1 SMRA0
SCK
Clock source
Prescaler division ratio /2048 /512 /128 /32 /8 /2 -- --
0
0
0 1
Output Output Output Output Output Output Output Input
Prescaler Prescaler Prescaler Prescaler Prescaler Prescaler System clock External clock
1
0 1
1
0
0 1
1
0 1
Figure 37 Serial Mode Register A (SMRA)
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HD404459 Series
Ports R5 and R6 are multiplexed with pins WU0-WU 7. The wakeup modes of these pins can be selected by the wakeup select register (WSR: $018). Even if wakeup input is valid, the R port functions normally (figure 38).
Wakeup select register (WSR: $018) Bit Initial value Read/Write Bit name 3 0 W WSR3 2 0 W WSR2 1 0 W WSR1 0 0 W WSR0
WSR0 0 1 WSR1 0 1 WSR2 0 1 WSR3 0 1
WU0 to WU3 control Invalid Valid WU4 to WU5 control Invalid Valid WU6 control Invalid Valid WU7 control Invalid Valid
Figure 38 Wakeup Select Register (WSR)
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HD404459 Series
Pull-Up MOS Transistor Control: A program-controlled pull-up MOS transistor is provided for each input/output pin other than input-only pins D 10, D11, R93, and RA 0-RA3. The on/off status of all these transistors is controlled by bit 3 (MIS3) of the miscellaneous register (MIS: $00C), and the on/off status of an individual transistor can also be controlled by the port data register (PDR) of the corresponding pin-- enabling on/off control of that pin alone (table 23 and figure 39). The on/off status of each transistor and the peripheral function mode of each pin can be set independently.
Miscellaneous register (MIS: $00C) Bit Initial value Read/Write Bit name 3 0 W MIS3 2 0 W MIS2 1 0 W MIS1 0 0 W MIS0
MIS3 0 1
Pull-up MOS on/off selection Off On
MIS2 0 1
CMOS buffer on/off selection for pin R43/SO On Off
MIS1
MIS0
tRC selection. Refer to figure 18 in the operation modes section.
Figure 39 Miscellaneous Register (MIS) How to Deal with Unused I/O Pins: I/O pins that are not needed by the user system (those that remain floating) must be connected to VCC to prevent LSI malfunctions due to noise. These pins must either be pulled up to VCC by their pull-up MOS transistors or by resistors of about 100 k.
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HD404459 Series
Prescalers
The MCU has two prescalers, S and W. See table 25 and figure 40. Both the timers A-D input clocks except external events and the serial transmit clock except the external clock are selected from the prescaler outputs, depending on corresponding mode registers.
32-kHz crystal oscillator
fX/8 Prescaler W
Timer A
Timer B fX/4 or fX/8 Timer C
Timer D System clock Clock selector
Prescaler S
Serial
Figure 40 Prescaler Output Supply Prescaler Operation Prescaler S: 11-bit counter that inputs a system clock signal. After being reset to $000 by MCU reset, prescaler S divides the system clock. Prescaler S keeps counting, except in watch and stop modes and at MCU reset. Prescaler W: Five-bit counter that inputs the X1 input clock signal (32-kHz crystal oscillation) divided. After being reset to $00 by MCU reset, prescaler W divides the input clock. Prescaler W can be reset by software. Table 25
Prescaler Prescaler S
Prescaler Operating Conditions
Input Clock System clock (in active and standby mode), Subsystem clock (in subactive mode) 32-kHz crystal oscillation Reset Conditions MCU reset Stop Conditions MCU reset, stop mode, watch mode
Prescaler W
MCU reset, software
MCU reset, stop mode
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HD404459 Series
Timers
The MCU has four timer/counters (A to D). Timer A: Timer B: Timer C: Timer D: Free-running timer Multifunction timer Multifunction timer Multifunction timer
Timer A is an 8-bit free-running timer. Timers B-D are 8-bit multifunction timers (table 26). The operating modes are selected by software. Table 26
Functions Clock source Prescaler S Prescaler W External event Timer functions Free-running Time-base Event counter Reload Watchdog Input capture Timer outputs Toggle 0 output 1 output PWM Note: -- means not available.
Timer Functions
Timer A Available Available -- Available Available -- -- -- -- -- -- -- -- Timer B Available -- Available Available -- Available Available -- -- Available Available Available -- Timer C Available -- -- Available -- -- Available Available -- Available Available Available Available Timer D Available -- Available Available -- Available Available -- Available Available Available Available Available
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HD404459 Series
Timer A Timer A Functions: Timer A (figure 41) has the following functions. * Free-running timer * Clock time-base
Timer A interrupt request flag (IFTA)
32.768-kHz oscillator
1/4
1/2 2 fW 1/2 tWcyc
fW tWcyc
Prescaler W (PSW)
/2 /8 / 16 / 32
Selector Internal data bus Selector Clock Timer counter A (TCA) Overflow
Selector
/2 /4 /8 / 32 / 128 / 512 / 1024 / 2048
System clock
o PER
Prescaler S (PSS)
3 Timer mode register A (TMA)
Figure 41 Block Diagram of Timer A Timer A Operations: * Free-running timer operation: The input clock for timer A is selected by timer mode register A (TMA: $008). Timer A is reset to $00 by MCU reset and incremented at each input clock. If an input clock is applied to timer A after it has reached $FF, an overflow is generated, and timer A is reset to $00. The overflow sets the timer A interrupt request flag (IFTA: $002, bit 0). Timer A continues to be incremented after reset to $00, and therefore it generates regular interrupts every 256 clocks. * Clock time-base operation: Timer A is used as a clock time-base by setting bit 3 (TMA3) of timer mode register A (TMA: $008) to 1. The prescaler W output is applied to timer A, and timer A generates interrupts at the correct timing based on the 32.768-kHz crystal oscillation. In this case, prescaler W and timer A can be reset to $00 by software.
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HD404459 Series
Registers for Timer A Operation: Timer A operating modes are set by the following registers. * Timer mode register A (TMA: $008): Four-bit write-only register that selects timer A's operating mode and input clock source (figure 42).
Timer mode register A (TMA: $008) Bit Initial value Read/Write Bit name 3 0 W TMA3 2 0 W TMA2 1 0 W TMA1 0 0 W TMA0
Source Input clock TMA3 TMA2 TMA1 TMA0 prescaler frequency Operating mode 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 0 0 1 1 Don't care PSS PSS PSS PSS PSS PSS PSS PSS PSW PSW PSW PSW PSW Not used PSW and TCA reset 2048tcyc 1024tcyc 512tcyc 128tcyc 32tcyc 8tcyc 4tcyc 2tcyc 32tWcyc 16tWcyc 8tWcyc 2tWcyc 1/2tWcyc Time-base mode Timer A mode
Note: 1. tWcyc = 244.14 s (when a 32.768-kHz crystal oscillator is used) 2. Timer counter overflow output period (seconds) = input clock period (seconds) x 256. 3. The division ratio must not be modified during time-base mode operation, otherwise an overflow cycle error will occur.
Figure 42 Timer Mode Register A (TMA)
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HD404459 Series
Timer B Timer B Functions: Timer B (figure 43) has the following functions. * Free-running/reload timer * External event counter * Timer output operation (toggle, 0, and 1 outputs)
Timer B interrupt request flag (IFTB) TOB Timer output control logic
Timer read register BU (TRBU) Timer read register BL (TRBL) Clock Timer/event counter B (TCB) Timer write register BU (TWBU) Timer write register BL (TWBL)
Timer output control
Overflow Internal data bus
Selector
/2 /4 /8 / 32 / 128 / 512
EVNB System clock o PER
Prescaler S (PSS) Free-running/ Reload control 3
/ 2048
Timer mode register B1 (TMB1)
2 Timer mode register B2 (TMB2)
Figure 43 Block Diagram of Timer B
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HD404459 Series
Timer B Operations: * Free-running/reload timer operation: The free-running/reload operation, input clock source, and prescaler division ratio are selected by timer mode register B1 (TMB1: $009). Timer B is initialized to the value set in timer write register B (TWBL: $00A, TWBU: $00B) by software and incremented by one at each clock input. If an input clock is applied to timer B after it has reached $FF, an overflow is generated. In this case, if the reload timer function is enabled, timer B is initialized to its initial value set in timer write register B; if the free-running timer function is enabled, the timer is initialized to $00 and then incremented again. The overflow sets the timer B interrupt request flag (IFTB: $002, bit 2). IFTB can be reset by software or MCU reset. Refer to figure 3 and table 1 for details. * External event counter operation: Timer B is used as an external event counter by selecting external event input as the input clock source. In this case, pin R33/EVNB must be set to EVNB by port mode register C (PMRC: $025). Timer B is incremented by one at each falling edge of signals input to pin EVNB. The other operations are basically the same as the free-running/ reload timer operation. * Timer output operation: The following three output modes can be selected for timer B by setting timer mode register B2 (TMB2: $013). Toggle 0 output 1 output By selecting the timer output mode, pin R30/TOB is set to TOB. The output from TOB is reset low by MCU reset. Toggle output: When toggle output mode is selected, the output level is inverted if a clock is input after timer B has reached $FF. By using this function and reload timer function, clock signals can be output at a required frequency for a buzzer. Refer to figure 44 for the output waveform. 0 output: When 0 output mode is selected, the output level is pulled low if a clock is input after timer B has reached $FF. Note that this function must be used only when the output level is high. 1 output: When 1 output mode is selected, the output level is set high if a clock is input after timer B has reached $FF. Note that this function must be used only when the output level is low.
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HD404459 Series
Toggle output waveform (timers B, C, and D) Free-running timer
256 clock cycles Reload timer
256 clock cycles
(256 - N) clock cycles (256 - N) clock cycles
PWM output waveform (timers C and D) T x (N + 1)
TMC13 = 0 TMD13 = 0 T x 256
T TMC13 = 1 TMD13 = 1
T x (256 - N) Note: The waveform is always fixed low when N = $FF. T: Input clock period to counter (figures 45, 53, and 60) N: The value of the timer write register (figures 55, 56, 62, and 63)
Figure 44 Timer Output Waveform Registers for Timer B Operation: By using the following registers, timer B operation modes are selected and the timer B count is read and written. Timer mode register B1 (TMB1: $009) Timer mode register B2 (TMB2: $013) Timer write register B (TWBL: $00A, TWBU: $00B) Timer read register B (TRBL: $00A, TRBU: $00B) Port mode register C (PMRC: $025)
* Timer mode register B1 (TMB1: $009): Four-bit write-only register that selects the free-running/reload timer function, input clock source, and the prescaler division ratio (figure 45). It is reset to $0 by MCU reset.
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HD404459 Series
The mode change of this register is valid from the second instruction execution cycle after the execution of the previous timer mode register B1 write instruction. Setting timer B's initialization by writing to timer write register B (TWBL: $00A, TWBU: $00B) must be done after a mode change becomes valid.
Timer mode register B1 (TMB1: $009) Bit Initial value Read/Write Bit name 3 0 W TMB13 2 0 W TMB12 1 0 W TMB11 0 0 W TMB10
TMB13 0 1
Free-running/reload timer selection Free-running timer Reload timer
TMB12 0
TMB11 0
TMB10 0 1
Input clock period and input clock source 2048tcyc 512tcyc 128tcyc 32tcyc 8tcyc 4tcyc 2tcyc R33/EVNB (external event input)
1
0 1
1
0
0 1
1
0 1
Figure 45 Timer Mode Register B1 (TMB1)
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HD404459 Series
* Timer mode register B2 (TMB2: $013): Two-bit read/write register that selects the timer B output mode (figure 46). It is reset to $0 by MCU reset.
Timer mode register B2 (TMB2: $013) Bit Initial value Read/Write Bit name 3 -- -- 2 -- -- 1 0 R/W 0 0 R/W TMB20
Not used Not used TMB21
TMB21 0
TMB20 0 1
R30/TOB mode selection R30 TOB TOB TOB R30 port Toggle output 0 output 1 output
1
0 1
Figure 46 Timer Mode Register B2 (TMB2) * Timer write register B (TWBL: $00A, TWBU: $00B): Write-only register consisting of a lower digit (TWBL) and an upper digit (TWBU) (figures 47 and 48). The lower digit is reset to $0 by MCU reset, but the upper digit value is undefined. Timer B is initialized by writing to timer write register B (TWBL: $00A, TWBU: $00B). In this case, the lower digit (TWBL) must be written to first, but writing only to the lower digit does not change the timer B value. Timer B is initialized to the value in timer write register B at the same time the upper digit (TWBU) is written to. When timer write register B is written to again and if the lower digit value needs no change, writing only to the upper digit initializes timer B.
Timer write register B (lower digit) (TWBL: $00A) Bit Initial value Read/Write Bit name 3 0 W TWBL3 2 0 W TWBL2 1 0 W TWBL1 0 0 W TWBL0
Figure 47 Timer Write Register B Lower Digit (TWBL)
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HD404459 Series
Timer write register B (upper digit) (TWBU: $00B) Bit Initial value Read/Write Bit name
3 2 1 0
Undefined Undefined Undefined Undefined W TWBU3 W TWBU2 W TWBU1 W TWBU0
Figure 48 Timer Write Register B Upper Digit (TWBU) * Timer read register B (TRBL: $00A, TRBU: $00B): Read-only register consisting of a lower digit (TRBL) and an upper digit (TRBU) that holds the count of the timer B upper digit. The upper digit (TRBU) must be read first, which will result in the count of the timer B upper digit to be obtained and the count of the timer B lower digit to be latched to the lower digit (TRBL). Then by reading TRBL, the count of timer B can be obtained when TRBU is read.
Timer read register B (lower digit) (TRBL: $00A) Bit Initial value Read/Write Bit name
3 2 1 0
Undefined Undefined Undefined Undefined R TRBL3 R TRBL2 R TRBL1 R TRBL0
Figure 49 Timer Read Register B Lower Digit (TRBL)
Timer read register B (upper digit) (TRBU: $00B) Bit Initial value Read/Write Bit name
3 2 1 0
Undefined Undefined Undefined Undefined R TRBU3 R TRBU2 R TRBU1 R TRBU0
Figure 50 Timer Read Register B Upper Digit (TRBU)
65
HD404459 Series
* Port mode register C (PMRC: $025): Write-only register that selects the R33/EVNB pin function (figure 51). It is reset to $0 by MCU reset.
Port mode register C (PMRC: $025) Bit Initial value Read/Write Bit name 3 -- -- 2 0 W 1 0 W 0 0 W
Not used PMRC2 PMRC1 PMRC0
PMRC0 0 1 PMRC1 0 1 PMRC2 0 1
R33/EVNB mode selection R33 EVNB R40/EVND mode selection R40 EVND D11/STOPC mode selection D11 STOPC
Figure 51 Port Mode Register C (PMRC)
66
HD404459 Series
Timer C Timer C Functions: Timer C (figure 52) has the following functions. Free-running/reload timer Watchdog timer Timer output operation (toggle, 0, 1, and PWM outputs)
System reset signal Watchdog on flag (WDON) Watchdog timer control logic
Timer C interrupt request flag (IFTC)
TOC
Timer output control logic Timer read register CU (TRCU) Timer output control Timer read register CL (TRCL) Clock Timer counter C (TCC) Overflow
Selector /2 /4 /8 /32 /128 /512 /1024 /2048
Timer write register CU (TWCU) Free-running /reload control 3 Timer mode register C1 (TMC1) Timer write register CL (TWCL)
System oPER clock
Prescaler S (PSS)
3 Timer mode register C2 (TMC2)
Figure 52 Block Diagram of Timer C
Internal data bus 67
HD404459 Series
Timer C Operations: * Free-running/reload timer operation: The free-running/reload operation, input clock source, and prescaler division ratio are selected by timer mode register C1 (TMC1: $00D). Timer C is initialized to the value set in timer write register C (TWCL: $00E, TWCU: $00F) by software and incremented by one at each clock input. If an input clock is applied to timer C after it has reached $FF, an overflow is generated. In this case, if the reload timer function is enabled, timer C is initialized to its initial value set in timer write register C; if the free-running timer function is enabled, the timer is initialized to $00 and then incremented again. The overflow sets the timer C interrupt request flag (IFTC: $003, bit 0). IFTC can be reset by software or MCU reset. Refer to figure 3 and table 1 for details. * Watchdog timer operation: Timer C is used as a watchdog timer for detecting out-of-control program routines by setting the watchdog on flag (WDON: $020, bit 1) to 1. If a program routine runs out of control and an overflow is generated, the MCU is reset. Program run can be controlled by initializing timer C by software before it reaches $FF. * Timer output operation: The following four output modes can be selected for timer C by setting timer mode register C2 (TMC2: $014). Toggle 0 output 1 output PWM output
By selecting the timer output mode, pin R31/TOC is set to TOC. The output from TOC is reset low by MCU reset. Toggle output: The operation is basically the same as that of timer-B's toggle output. 0 output: The operation is basically the same as that of timer-B's 0 output. 1 output: The operation is basically the same as that of timer-B's 1 output. PWM output (figure 44): When PWM output mode is selected, timer C provides the variable-duty pulse output function. The output waveform differs depending on the contents of timer mode register C1 (TMC1: $00D) and timer write register C (TWCL: $00E, TWCU: $00F).
Registers for Timer C Operation: By using the following registers, timer C operation modes are selected and the timer C count is read and written. Timer mode register C1 (TMC1: $00D) Timer mode register C2 (TMC2: $014) Timer write register C (TWCL: $00E, TWCU: $00F) Timer read register C (TRCL: $00E, TRCU: $00F)
* Timer mode register C1 (TMC1: $00D): Four-bit write-only register that selects the free-running/ reload timer function, input clock source, and prescaler division ratio (figure 53). It is reset to $0 by MCU reset.
68
HD404459 Series
The mode change of this register is valid from the second instruction execution cycle after the execution of the previous timer mode register C1 write instruction. Setting timer C's initialization by writing to timer write register C (TWCL: $00E, TWCU: $00F) must be done after a mode change becomes valid.
Timer mode register C1 (TMC1: $00D) Bit Initial value Read/Write Bit name 3 0 W TMC13 2 0 W TMC12 1 0 W TMC11 0 0 W TMC10
TMC13 0 1
Free-running/reload timer selection Free-running timer Reload timer
TMC12 0
TMC11 0
TMC10 0 1
Input clock period 2048tcyc 1024tcyc 512tcyc 128tcyc 32tcyc 8tcyc 4tcyc 2tcyc
1
0 1
1
0
0 1
1
0 1
Figure 53 Timer Mode Register C1 (TMC1)
69
HD404459 Series
* Timer mode register C2 (TMC2: $014): Three-bit read/write register that selects the timer C output mode (figure 54). It is reset to $0 by MCU reset.
Timer mode register C2 (TMC2: $014) Bit Initial value Read/Write Bit name 3 -- -- 2 0 R/W 1 0 R/W TMC21 0 0 R/W TMC20
Not used TMC22
TMC22 0
TMC21 0
TMC20 0 1
R31/TOC mode selection R31 TOC TOC TOC TOC R31 port Toggle output 0 output 1 output Not used
1
0 1
1
0
0 1
1
0 1 TOC PWM output
Figure 54 Timer Mode Register C2 (TMC2) * Timer write register C (TWCL: $00E, TWCU: $00F): Write-only register consisting of a lower digit (TWCL) and an upper digit (TWCU) (figures 55 and 56). The operation of timer write register C is basically the same as that of timer write register B (TWBL: $00A, TWBU: $00B).
Timer write register C (lower digit) (TWCL: $00E) Bit Initial value Read/Write Bit name 3 0 W TWCL3 2 0 W TWCL2 1 0 W TWCL1 0 0 W TWCL0
Figure 55 Timer Write Register C Lower Digit (TWCL)
70
HD404459 Series
Timer write register C (upper digit) (TWCU: $00F) Bit Initial value Read/Write Bit name
3 2 1 0
Undefined Undefined Undefined Undefined W TWCU3 W TWCU2 W TWCU1 W TWCU0
Figure 56 Timer Write Register C Upper Digit (TWCU) * Timer read register C (TRCL: $00E, TRCU: $00F): Read-only register consisting of a lower digit (TRCL) and an upper digit (TRCU) that holds the count of the timer C upper digit(figures 57 and 58). The operation of timer read register C is basically the same as that of timer read register B (TRBL: $00A, TRBU:$00B).
Timer read register C (lower digit) (TRCL: $00E) Bit Initial value Read/Write Bit name
3 2 1 0
Undefined Undefined Undefined Undefined R TRCL3 R TRCL2 R TRCL1 R TRCL0
Figure 57 Timer Read Register C Lower Digit (TRCL)
Timer read register C (upper digit) (TRCU: $00F) Bit Initial value Read/Write Bit name
3 2 1 0
Undefined Undefined Undefined Undefined R TRCU3 R TRCU2 R TRCU1 R TRCU0
Figure 58 Timer Read Register C Upper Digit(TRCU) Timer D Timer D Functions: Timer D (figures 59 (A) and (B)) has the following functions. Free-running/reload timer External event counter Timer output operation (toggle, 0, 1, and PWM outputs) Input capture timer
71
HD404459 Series
Timer D interrupt request flag (IFTD) TOD Timer output control logic
Timer read register DU (TRDU)
Timer output control Timer read register DL (TRDL) Clock Timer counter D (TCD) Overflow
Selector EVND Edge detection logic oPER
/2048
/2 /4 /8 /32 /128 /512
Free-running/ Reload control 3
Timer write register DL (TWDL)
System clock
Prescaler S (PSS)
Timer mode register D1 (TMD1) 3 Timer mode register D2 (TMD2) Edge detection control
2 Edge detection selection register 2 (ESR2)
Figure 59(A) Block Diagram of Timer D (Free-Running/Reload Timer)
72
Internal data bus
Timer write register DU (TWDU)
HD404459 Series
Input capture status flag (ICSF) Input capture error flag (ICEF) Error control logic Timer D interrupt request flag (IFTD)
Timer read register DU (TRDU) Timer read register DL (TRDL) EVND Edge detection logic Read signal Clock Input capture timer control Internal data bus 73 Timer counter D (TCD) Overflow
Selector
3 Timer mode register D1 (TMD1)
System clock
oPER Prescaler S (PSS) Timer mode register D2 (TMD2) Edge detection control 2 Edge detection selection register 2 (ESR2)
Figure 59(B) Block Diagram of Timer D (Input Capture Timer)
/2048
/2 /4 /8 /32 /128 /512
HD404459 Series
Timer D Operations: * Free-running/reload timer operation: The free-running/reload operation, input clock source, and prescaler division ratio are selected by timer mode register D1 (TMD1: $010). Timer D is initialized to the value set in timer write register D (TWDL: $011, TWDU: $012) by software and incremented by one at each clock input. If an input clock is applied to timer D after it has reached $FF, an overflow is generated. In this case, if the reload timer function is enabled, timer D is initialized to its initial value set in timer write register D; if the free-running timer function is enabled, the timer is initialized to $00 and then incremented again. The overflow sets the timer D interrupt request flag (IFTD: $001, bit 2). IFTD can be reset by software or MCU reset. Refer to figure 3 and table 1 for details. * External event counter operation: Timer D is used as an external event counter by selecting the external event input as an input clock source. In this case, pin R40/EVND must be set to EVND by port mode register C (PMRC: $025). Either falling or rising edge, or both falling and rising edges of input signals can be selected as the external event detection edge by detection edge select register 2 (ESR2: $027). When both rising and falling edges detection is selected, the time between the falling edge and rising edge of input signals must be 2t cyc or longer. Timer D is incremented by one at each detection edge selected by detection edge select register 2 (ESR2: $027). The other operation is basically the same as the free-running/reload timer operation. * Timer output operation: The following four output modes can be selected for timer D by setting timer mode register D2 (TMD2: $015). Toggle 0 output 1 output PWM output
By selecting the timer output mode, pin R32/TOD is set to TOD. The output from TOD is reset low by MCU reset. Toggle output: The operation is basically the same as that of timer-B's toggle output. 0 output: The operation is basically the same as that of timer-B's 0 output. 1 output: The operation is basically the same as that of timer-B's 1 output. PWM output: The operation is basically the same as that of timer-C's PWM output.
* Input capture timer operation: The input capture timer counts the clock cycles between trigger edges input to pin EVND. Either falling or rising edge, or both falling and rising edges of input signals can be selected as the trigger input edge by detection edge select register 2 (ESR2: $027).
74
HD404459 Series
When a trigger edge is input to EVND, the count of timer D is written to timer read register D (TRDL: $011, TRDU: $012), and the timer D interrupt request flag (IFTD: $001, bit 2) and the input capture status flag (ICSF: $021, bit 0) are set. Timer D is reset to $00, and then incremented again. While ICSF is set, if a trigger input edge is applied to timer D, or if timer D generates an overflow, the input capture error flag (ICEF: $021, bit 1) is set. ICSF and ICEF can be reset to 0 by MCU reset or by writing 0. By selecting the input capture operation, pin R3 2/TOD is set to R3 2 and timer D is reset to $00. Registers for Timer D Operation: By using the following registers, timer D operation modes are selected and the timer D count is read and written. Timer mode register D1 (TMD1: $010) Timer mode register D2 (TMD2: $015) Timer write register D (TWDL: $011, TWDU: $012) Timer read register D (TRDL: $011, TRDU: $012) Port mode register C (PMRC: $025) Detection edge select register 2 (ESR2: $027)
* Timer mode register D1 (TMD1: $010): Four-bit write-only register that selects the free-running/reload timer function, input clock source, and the prescaler division ratio (figure 60). It is reset to $0 by MCU reset. The mode change of this register is valid from the second instruction execution cycle after the execution of the previous timer mode register D1 (TMD1: $010) write instruction. Setting timer D's initialization by writing to timer write register D (TWDL: $011, TWDU: $012) must be done after a mode change becomes valid. When selecting the input capture timer operation, select the internal clock as the input clock source.
75
HD404459 Series
Timer mode register D1 (TMD1: $010) Bit Initial value Read/Write Bit name 3 0 W TMD13 2 0 W TMD12 1 0 W TMD11 0 0 W TMD10
TMD13 0 1
Free-running/reload timer selection Free-running timer Reload timer
TMD12 0
TMD11 0
TMD10 0 1
Input clock period and input clock source 2048tcyc 512tcyc 128tcyc 32tcyc 8tcyc 4tcyc 2tcyc R40/EVND (external event input)
1
0 1
1
0
0 1
1
0 1
Figure 60 Timer Mode Register D1 (TMD1)
76
HD404459 Series
* Timer mode register D2 (TMD2: $015): Four-bit read/write register that selects the timer D output mode and input capture operation (figure 61). It is reset to $0 by MCU reset.
Timer mode register D2 (TMD2: $015) Bit Initial value Read/Write Bit name 3 0 R/W TMD23 2 0 R/W TMD22 1 0 R/W TMD21 0 0 R/W TMD20
TMD23 0
TMD22 0
TMD21 0
TMD20 0 1
R32/TOD mode selection R32 TOD TOD TOD TOD R32 port Toggle output 0 output 1 output Not used
1
0 1
1
0
0 1
1
0 1 TOD R32 PWM output Input capture (R32 port)
1
Don't care Don't care Don't care
Figure 61 Timer Mode Register D2(TMD2) * Timer write register D (TWDL: $011, TWDU: $012): Write-only register consisting of a lower digit (TWDL) and an upper digit (TWDU) (figures 62 and 63). The operation of timer write register D is basically the same as that of timer write register B (TWBL: $00A, TWBU: $00B).
Timer write register D (lower digit) (TWDL: $011) Bit Initial value Read/Write Bit name 3 0 W TWDL3 2 0 W TWDL2 1 0 W TWDL1 0 0 W TWDL0
Figure 62 Timer Write Register D Lower Digit (TWDL)
77
HD404459 Series
Timer write register D (upper digit) (TWDU: $012) Bit Initial value Read/Write Bit name
3 2 1 0
Undefined Undefined Undefined Undefined W TWDU3 W TWDU2 W TWDU1 W TWDU0
Figure 63 Timer Write Register D Upper Digit (TWDU) * Timer read register D (TRDL: $011, TRDU: $012): Read-only register consisting of a lower digit (TRDL) and an upper digit (TRDU) (figures 64 and 65). The operation of timer read register D is basically the same as that of timer read register B (TRBL: $00A, TRBU: $00B). When the input capture timer operation is selected and if the count of timer D is read after a trigger is input, either the lower or upper digit can be read first.
Timer read register D (lower digit) (TRDL: $011) Bit Initial value Read/Write Bit name
3 2 1 0
Undefined Undefined Undefined Undefined R TRDL3 R TRDL2 R TRDL1 R TRDL0
Figure 64 Timer Read Register D Lower Digit (TRDL)
Timer read register D (upper digit) (TRDU: $012) Bit Initial value Read/Write Bit name
3 2 1 0
Undefined Undefined Undefined Undefined R TRDU3 R TRDU2 R TRDU1 R TRDU0
Figure 65 Timer Read Register D Upper Digit (TRDU) * Port mode register C (PMRC: $025): Write-only register that selects R40/EVND pin function (figure 51). It is reset to $0 by MCU reset.
78
HD404459 Series
* Detection edge select register 2 (ESR2: $027): Write-only register that selects the detection edge of signals input to pin EVND (figure 66). It is reset to $0 by MCU reset.
Detection edge register 2 (ESR2: $027) Bit Initial value Read/Write Bit name 3 0 W ESR23 2 0 W 1 -- -- 0 -- --
ESR22 Not used Not used
ESR23 0
ESR22 0 1
EVND detection edge No detection Falling-edge detection Rising-edge detection Double-edge detection*
1
0 1
Note: * Both falling and rising edges are detected.
Figure 66 Detection Edge Select Register 2 (ESR2)
79
HD404459 Series
Notes on Use When using the timer output as PWM output, note the following point. From the update of the timer write register until the occurrence of the overflow interrupt, the PWM output differs from the period and duty settings, as shown in table 27. The PWM output should therefore not be used until after the overflow interrupt following the update of the timer write register. After the overflow, the PWM output will have the set period and duty cycle. Table 27 PWM Output following Update of Timer Write Register
PWM Output Mode Free running Timer Write Register is Updated during High PWM Output
Timer write register updated to value N
Timer Write Register is Updated during Low PWM Output
Timer write register updated to value N
Interrupt request
Interrupt request
T x (255 - N) T x (N + 1)
T x (N' + 1) T x (255 - N) T x (N + 1)
Reload
Timer write register updated to value N
Interrupt request
Timer write register updated to value N
Interrupt request
T
T x (255 - N)
T
T T x (255 - N) T
80
HD404459 Series
Serial Interface
The MCU has a serial interface (figure 67). The serial interface serially transfers or receives 8-bit data, and includes the following features. * Multiple transmit clock sources External clock Internal prescaler output clock System clock * Output level control in idle states Five registers, an octal counter, and a multiplexer are also configured for the serial interface as follows. Serial data register (SRL: $006, SRU: $007) Serial mode register A (SMRA: $005) Serial mode register B (SMRB: $028) Port mode register A (PMRA: $004) Miscellaneous register (MIS: $00C) Octal counter (OC) Selector
81
HD404459 Series
Octal counter (OC) Idle controller SCK I/O controller SI Transfer control signal Internal data bus Clock Serial data register (SR) Serial interrupt request flag (IFS)
SO
Selector 3 /2 /8 /32 /128 /512 /2048 Serial mode register A (SMRA)
System clock
PER
Prescaler S (PSS)
Selector
1/2
1/2
Serial mode register B (SMRB)
Figure 67 Serial Interface Block Diagram Serial Interface Operation Selecting and Changing the Operating Mode: To select an operating mode, use one of these combinations of port mode register A (PMRA: $004) and serial mode register A (SMRA: $005) settings (table 28); to change the operating mode of the serial interface, always initialize the serial interface internally by writing data to serial mode register A. Note that the serial interface is initialized by writing data to serial mode register A. Refer to the following section, Registers for Serial Interface, for details. Pin Setting: The R41/SCK pin is controlled by writing data to serial mode register A (SMRA: $005). Pins R4 2/SI and R4 3/SO are controlled by writing data to port mode register A (PMRA: $004). Refer to the following section, Registers for Serial Interface, for details. Transmit Clock Source Setting: The transmit clock source of the serial interface is set by writing data to serial mode register A (SMRA: $005) and serial mode register B (SMRB: $028). Refer to the following section, Registers for Serial Interface, for details. Data Setting: Transmit data of the serial interface is set by writing data to the serial data register (SRL: $006, SRU: $007). Receive data of the serial interface is obtained by reading the contents of the serial data register. The serial data is shifted by each serial interface transmit clock and is input from or output to an external system.
82
HD404459 Series
The output level of the SO pins is undefined until the first data of each serial interface is output after MCU reset, or until the output level control in idle states is performed. Transfer Control: The serial interface is activated by the STS instruction. The octal counter is reset to 000 by the STS instruction and is incremented at the rising edge of the transmit clock for the serial interface. When the eighth transmit clock signal is input or when serial transmission/reception is discontinued, the octal counter is reset to 000, the serial interrupt request flag (IFS: $023, bit 0) for serial interface is set, and the transfer stops. When the prescaler output is selected as the transmit clock of the serial interface, the transmit clock frequency is selected as 4tcyc to 8192tcyc by setting bits 0 to 2 (SMRA0-SMRA2) of serial mode register A (SMRA: $005) and bit 0 (SMRB0) of serial mode register B (SMRB: $028) (table 29). Table 28
SMRA Bit 3 1
Serial Interface Operating Mode
PMRA Bit 1 0 Bit 0 0 1 1 0 1 Operating Mode Continuous clock output mode Transmit mode Receive mode Transmit/receive mode
Table 29
SMRB Bit 0 0
Serial Transmit Clock (Prescaler Output)
SMRA Bit 2 0 Bit 1 0 Bit 0 0 1 1 0 1 1 0 0 1 Prescaler Division Ratio / 2048 / 512 / 128 / 32 /8 /2 / 4096 / 1024 / 256 / 64 / 16 /4 Transmit Clock Frequency 4096t cyc 1024t cyc 256t cyc 64t cyc 16t cyc 4t cyc 8192t cyc 2048t cyc 512t cyc 128t cyc 32t cyc 8t cyc
1
0
0
0 1
1
0 1
1
0
0 1
83
HD404459 Series
Operating States: The serial interface has the following operating states, which allow transitions to occur between them (figure 68). STS wait state Transmit clock wait state Transfer state Continuous clock output state (only in internal clock mode)
External clock mode
STS wait state (Octal counter = 000, transmit clock disabled) 00 MCU reset
SMRA write
04 01 STS instruction 02 Transmit clock
06 SMRA write (IFS 1)
Transmit clock wait state (Octal counter = 000)
Transfer state (Octal counter = 000)
03 8 transmit clocks
05 STS instruction (IFS 1)
Internal clock mode
STS wait state (Octal counter = 000, transmit clock disabled)
SMRA write 18 Continuous clock output state (PMRA 0, 1 = 0, 0)
10
MCU reset
13 SMRA write 14 11 STS instruction
8 transmit clocks
16 SMRA write (IFS 1)
Transmit clock 17
12 Transmit clock Transmit clock wait state (Octal counter = 000) 15 STS instruction (IFS 1) Transfer state (Octal counter = 000)
Note: Refer to the Operating States section for the explanations on the corresponding encircled numbers.
Figure 68 Serial Interface State Transitions * STS wait state: The serial interface enters STS wait state by MCU reset (00 and 10 in figure 68). In STS wait state, the serial interface is initialized and the transmit clock is ignored. If the STS instruction is then executed (01 and 11), the serial interface enters transmit clock wait state.
84
HD404459 Series
* Transmit clock wait state: Transmit clock wait state is the period between the STS execution and the falling edge of the first transmit clock. In transmit clock wait state, input of the transmit clock (02 and 12) increments the octal counter, shifts the serial data register (SRL: $006, SRU: $007), and enters the serial interface in transfer state. However, note that if continuous clock output state is selected in internal clock mode, the serial interface does not enter transfer state but enters continuous clock output state (17). The serial interface enters STS wait state by writing data to serial mode register A (SMRA: $005) (04 and 14) in transmit clock wait state. * Transfer state: Transfer state is the period between the falling edge of the first clock and the rising edge of the eighth clock. In transfer state, the input of eight clocks or the execution of the STS instruction sets the octal counter to 000, and the serial interface enters another state. When the STS instruction is executed (05 and 15), transmit clock wait state is entered. When eight clocks are input, transmit clock wait state is entered (03) in external clock mode, or STS wait state is entered (13) in internal clock mode. In internal clock mode, the transmit clock stops after outputting eight clocks. In transfer state, writing data to serial mode register A (SMRA: $005) (06 and 16) initializes the serial interface, and STS wait state is entered. If the state changes from transfer to another state, the serial interrupt request flag (IFS: $023, bit 0) is set by the octal counter that is reset to 000. * Continuous clock output state (only in internal clock mode): Continuous clock output state is entered only in internal clock mode. In this state, the serial interface does not transmit/receive data but only outputs the transmit clock from the SCK pin. When bits 0 and 1 (PMRA0, PMRA1) of port mode register A (PMRA: $004) are 00 in transmit clock wait state and if the transmit clock is input (17), the serial interface enters continuous clock output state. If serial mode register A (SMRA: $005) is written to in continuous clock output mode (18), STS wait state is entered. Output Level Control in Idle States: When the serial interface is in STS instruction wait state and transmit clock wait state, the output of serial output pin SO can be controlled by setting bit 1 (SMRB1) of serial mode register B (SMRB: $028) to 0 or 1. See figure 69 for an output level control example of the serial interface. Note that the output level cannot be controlled in transfer state.
85
,
HD404459 Series
Transmit clock wait state State STS wait state Transfer state MCU reset Port selection PMRA write SMRA write SMRB write SRL, SRU write External clock selection Output level control in idle states Data write for transmission STS instruction SCK pin (input) SO pin Undefined LSB IFS External clock mode Transmit clock wait state State STS wait state Transfer state MCU reset Port selection PMRA write SMRA write SMRB write SRL, SRU write Internal clock selection Output level control in idle states Data write for transmission STS instruction SCK pin (output) SO pin Undefined LSB IFS Internal clock mode
Transmit clock wait state STS wait state
Dummy write for state transition Output level control in idle states
MSB
Flag reset at transfer completion
STS wait state
Output level control in idle states
MSB
Flag reset at transfer completion
Figure 69 Example of Serial Interface Operation Sequence
86
HD404459 Series
Transmit Clock Error Detection (In External Clock Mode): The serial interface will malfunction if a spurious pulse caused by external noise conflicts with a normal transmit clock during transfer. A transmit clock error of this type can be detected (figure 70). If more than eight transmit clocks are input in transfer state, at the eighth clock including a spurious pulse by noise, the octal counter reaches 000, the serial interrupt request flag (IFS: $023, bit 0) is set, and transmit clock wait state is entered. At the falling edge of the next normal clock signal, the transfer state is again entered. After the transfer is completed and IFS is reset, writing to serial mode register A (SMRA: $005) then changes the state from transfer to STS wait. However, during the time the serial interface was in the transfer state with the serial interrupt request flag (IFS: $023, bit 0) being set again, the error can be detected. Notes on Use: * Initialization after writing to registers: If port mode register A (PMRA: $004) is written to in transmit clock wait state or in transfer state, the serial interface must be initialized by writing to serial mode register A (SMRA: $005) again. * Serial interrupt request flag (IFS: $023, bit 0) set: For the serial interface, if the state is changed from transfer state to another by writing to serial mode register A (SMRA: $005) or executing the STS instruction during the first low pulse of the transmit clock, the serial interrupt request flag (IFS: $023, bit 0) is not set. To set the serial interrupt request flag (IFS: $023, bit 0), a serial mode register A (SMRA: $005) write or STS instruction execution must be programmed to be executed after confirming that the SCK pin is at 1, that is, after executing the input instruction to port R4.
87

HD404459 Series
IFS 0 Transmit clock wait state State SCK pin (input) Noise 1 2 3 4 SMRA write IFS
Transfer completion (IFS 1)
Interrupts inhibited
SMRA write
IFS = 1?
Yes
Transmit clock error processing
No
Normal termination
Transmit clock error detection flowchart
Transmit clock wait state Transfer state
Transfer state
5
6
7 8 Transfer state has been entered by the transmit clock error. When SMRA is written, IFS is set.
Flag set because octal counter reaches 000.
Flag reset at transfer completion.
Transmit clock error detection procedures
Figure 70 Transmit Clock Error Detection
88
HD404459 Series
Registers for Serial Interface The serial interface operation is selected, and serial data is read and written by the following registers. Serial mode register A (SMRA: $005) Serial mode register B (SMRB: $028) Serial data register (SRL: $006, SRU: $007) Port mode register A (PMRA: $004) Miscellaneous register (MIS: $00C)
Serial Mode Register A (SMRA: $005): This register has the following functions (figure 71). * * * * R4 1/SCK pin function selection Transmit clock selection Prescaler division ratio selection Serial interface initialization
Serial mode register A (SMRA: $005) is a 4-bit write-only register. It is reset to $0 by MCU reset. A write signal input to serial mode register A (SMRA: $005) discontinues the input of the transmit clock to the serial data register (SRL: $006, SRU: $007) and octal counter, and the octal counter is reset to 000. Therefore, if a write is performed during data transfer, the serial interrupt request flag (IFS: $023, bit 0) is set. Written data is valid from the second instruction execution cycle after the write operation, so the STS instruction must be executed at least two cycles after that.
89
HD404459 Series
Serial mode register A (SMRA: $005) Bit Initial value Read/Write Bit name 3 0 W SMRA3 2 0 W 1 0 W 0 0 W
SMRA2 SMRA1 SMRA0
SMRA3 0 1
R41/SCK mode selection R41 SCK
SMRA2 0
SMRA1 SMRA0 0 0 1 1 0 1
SCK Output
Clock source Prescaler
Prescaler division ratio Refer to table 29
1
0
0 1
1
0 1
Output Input
System clock External clock
-- --
Figure 71 Serial Mode Register A (SMRA) Serial Mode Register B (SMRB: $028): This register has the following functions (figure 72). * Prescaler division ratio selection * Output level control in idle states Serial mode register B (SMRB: $028) is a 2-bit write-only register. It cannot be written during data transfer. By setting bit 0 (SMRB0) of this register, the prescaler division ratio is selected. Only bit 0 (SMRB0) can be reset to 0 by MCU reset. By setting bit 1 (SMRB1), the output level of the SO pin is controlled in idle states of the serial interface. The output level changes at the same time that SMRB1 is written to.
90
HD404459 Series
Serial mode register B (SMRB: $028) Bit Initial value Read/Write Bit name 3 -- -- 2 -- --
1 Undefined W
0 0 W SMRB0
Not used Not used SMRB1
SMRB1 0 1
Output level control in idle states Low level High level
SMRB0 0 1
Serial clock division ratio Prescaler output divided by 2 Prescaler output divided by 4
Figure 72 Serial Mode Register B (SMRB) Serial Data Register (SRL: $006, SRU: $007): This register has the following functions (figures 73 and 74). * Transmission data write and shift * Receive data shift and read Writing data in this register is output from the SO pin, LSB first, synchronously with the falling edge of the transmit clock (figure 75); data is input, LSB first, through the SI pin at the rising edge of the transmit clock. Data cannot be read or written during serial data transfer. If a read/write occurs during transfer, the accuracy of the resultant data cannot be guaranteed.
Serial data register (lower digit) (SRL: $006) Bit Initial value Read/Write Bit name
3 2 1 0
Undefined Undefined Undefined Undefined R/W SR3 R/W SR2 R/W SR1 R/W SR0
Figure 73 Serial Data Register Lower Digit (SRL)
91
HD404459 Series
Serial data register (upper digit) (SRU: $007) Bit Initial value Read/Write Bit name
3 2 1 0
Undefined Undefined Undefined Undefined R/W SR7 R/W SR6 R/W SR5 R/W SR4
Figure 74 Serial Data Register Upper Digit (SRU)
Transmit clock 1 Serial output data LSB 2 3 4 5 6 7 8 MSB
Serial input data latch timing
Figure 75 Serial Interface Output Timing
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HD404459 Series
Port Mode Register A (PMRA: $004): This register has the following functions (figure 76). * R4 2/SI pin function selection * R4 3/SO pin function selection Port mode register A (PMRA: $004) is a 2-bit write-only register, and is reset to $0 by MCU reset.
Port mode register A (PMRA: $004) Bit Initial value Read/Write Bit name 3 -- -- 2 -- -- 1 0 W 0 0 W
Not used Not used PMRA1 PMRA0
PMRA0 0 1 PMRA1 0 1
R43/SO mode selection R43 SO R42/SI mode selection R42 SI
Figure 76 Port Mode Register A (PMRA)
93
HD404459 Series
Miscellaneous Register (MIS: $00C): This register has the following functions (figure 77). * R4 3/SO pin PMOS control Miscellaneous register (MIS: $00C) is a 4-bit write-only register and is reset to $0 by MCU reset.
Miscellaneous register (MIS: $00C) Bit Initial value Read/Write Bit name 3 0 W MIS3 2 0 W MIS2 1 0 W MIS1 0 0 W MIS0
MIS1 0
MIS0 0 1
tRC 0.12207 ms 7.8125 ms 62.5 ms Not used
1
0 1
MIS2 0 1 MIS3 0 1
R43/SO PMOS on/off selection On Off Pull-up MOS on/off selection Off On
Figure 77 Miscellaneous Register (MIS)
94
HD404459 Series
Comparator
The comparator (figure 78) compares an analog input voltage with a reference voltage. Either a 16-level internal or external reference power supply can be selected. The voltage comparison is started by writing 1 to the comparator start flag (CMSF: $020, bit 2), and is completed after 4t cyc. The comparison result is stored into bit 3 (CER: $017, bit 3) of the comparator enable register, and can be read by the bit test instruction (TM or TMD). The comparison result must be read after confirming that the comparator start flag (CMSF: $020, bit 2) is at 0 (figure 79).
Internal data bus
4 Comparator control register (CCR) 4
1 Comparator start flag (CMSF) 1
3
1
Comparator enable register (CER)
1 2
Selector
R93/VCref COMP
RA0/COMP0 RA1/COMP1 RA2/COMP2 RA3/COMP3
Selector
Figure 78 Block Diagram of Comparator
Selector
95
HD404459 Series
Comparator start flag Write cycle Internal system clock Comparator start flag (CMSF) Voltage comparison result (CER3) 4tcyc (RA port must not be used)
Figure 79 Comparator Operation Timing
96
HD404459 Series
Comparator Control Register (CCR: $016): Four-bit write-only register which selects a 16-level internal reference power supply (figure 80). The comparator control register (CCR: $016) is reset to $0 by MCU reset.
Comparator control register (CCR: $016) Bit Initial value Read/Write Bit name 3 0 W CCR3 2 0 W CCR2 1 0 W CCR1 0 0 W CCR0
CCR3 0
CCR2 0
CCR1 0
CCR0 0 1
Reference power supply selection 1/17 VCC 2/17 VCC 3/17 VCC 4/17 VCC 5/17 VCC 6/17 VCC 7/17 VCC 8/17 VCC 9/17 VCC 10/17 VCC 11/17 VCC 12/17 VCC 13/17 VCC 14/17 VCC 15/17 VCC 16/17 VCC
1
0 1
1
0
0 1
1
0 1
1
0
0
0 1
1
0 1
1
0
0 1
1
0 1
Figure 80 Comparator Control Register (CCR) Comparator Enable Register (CER: $017): This register consists of a 3-bit write-only register and a 1-bit read-only register. It selects the analog input pins and reference voltage, and indicates the voltage comparison result. The comparison result output is 0 when an analog input voltage is lower than the reference voltage, and is 1 when an analog input voltage is higher than the reference voltage. The comparison result is read by the bit test instruction (TM or TMD). The comparator enable register (CER: $017) is reset to $0 by MCU reset.
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HD404459 Series
Comparator enable register (CER: $017) Bit Initial value Read/Write Bit name 3 0 R CER3 2 0 W CER2 1 0 W CER1 0 0 W CER0
CER1 0
CER0 0 1
Analog input mode selection COMP0 COMP1 COMP2 COMP3
1
0 1
CER2 0 1 CER3 0 1
Reference power supply selection External reference power supply Internal reference power supply Voltage comparison result Analog input voltage is lower than reference voltage Analog input voltage is higher than reference voltage
Figure 81 Comparator Enable Register (CER) Comparator Start Flag (CMSF: $020, Bit 2): Starts the comparator operation. The comparator starts the voltage comparison by writing 1 to the comparator start flag (CMSF: $020, bit 2), and automatically completes the voltage comparison after 4tcyc. The comparator start flag is then reset to 0. The comparison result must be read after confirming that the comparator start flag is at 0. The comparator start flag is reset to 0 by MCU reset. Notes on Use: RA0/COMP0-RA3/COMP3 pins are used only for the comparator during voltage comparison. These pins cannot be used for R ports. The comparator operates only in the active and standby modes. The switch for the internal power supply is turned on when the internal power supply is selected. The switch is turned off except in active and standby modes. When the external power supply is used for a reference voltage, R93/VCref must not be used as an R port.
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HD404459 Series
Notes on Mounting
Assemble all parts including the HD404458/HD404459 on a board, noting the points described below. Between the VCC and GND lines, connect capacitors designed for use in ordinary power supply circuits. An example connection is described in figure 82. No resistors can be inserted in series in the power supply circuit, so the capacitors should be connected in parallel. The capacitors are a large capacitance C1 and a small capacitance C2.
VCC C1 C2
VCC
GND
GND
Figure 82 Example of Connections
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HD404459 Series
Programmable ROM (HD4074459)
The HD4074459 is a ZTAT TM microcomputer with a built-in PROM that can be programmed in PROM mode. PROM Mode Pin Description
Pin No. FP-64A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 MCU Mode Pin Name RA0/COMP0 RA 1/COMP1 RA 2/COMP2 RA 3/COMP3 TEST OSC 1 OSC 2 GND X2 X1 RESET D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11/STOPC VCC R0 0/INT0 R0 1/INT1 R0 2/INT2 R0 3/INT3 I/O I I I I I I O -- O I I I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I I -- I/O I/O I/O I/O GND RESET O0 O1 O2 O3 O4 O5 O6 O7 A13 A14 VPP A9 VCC M0 M1 I I I I/O I/O I/O I/O I/O I/O I/O I/O I I I I GND -- TEST VCC I PROM Mode Pin Name I/O Pin No. FP-64A 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 MCU Mode Pin Name R1 0 R1 1 R12 R1 3 R2 0 R2 1 R2 2 R2 3 R3 0/TOB R3 1/TOC R3 2/TOD R3 3/EVNB R4 0/EVND R4 1/SCK R4 2/SI R4 3/SO R5 0/(WU0) R5 1/(WU1) R5 2/(WU2) R5 3/(WU3) R6 0/(WU4) R6 1/(WU5) R6 2/(WU6) R6 3/(WU7) R7 0 R7 1 R7 2 R7 3 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O CE OE VCC VCC A1 A2 A3 A4 I I I I I I PROM Mode Pin Name A5 A6 A7 A8 A0 A10 A11 A12 I/O I I I I I I I I
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HD404459 Series
Pin No. FP-64A 57 58 59 60 MCU Mode Pin Name R8 0 R8 1 R8 2 R8 3 I/O I/O I/O I/O I/O PROM Mode Pin Name O4 O3 O2 O1 I/O I/O I/O I/O I/O Pin No. FP-64A 61 62 63 64 MCU Mode Pin Name R9 0 R9 1 R9 2 R9 3/VCref I/O I/O I/O I/O I PROM Mode Pin Name O0 VCC I/O I/O
Notes: 1. I/O: Input/output pin, I: Input pin, O: Output pin 2. Each of O0-O4 has two pins; before using them, each pair must be connected together.
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HD404459 Series
Programming the Built-In PROM
The MCU's built-in PROM is programmed in PROM mode. This PROM mode is set by pulling TEST, M0, and M1 low, and RESET high (figure 83). In PROM mode, the MCU does not operate, but it can be programmed in the same way as any other commercial 27256-type EPROM using a standard PROM programmer and a 64-to-28-pin socket adapter. Refer to table 31 for the Recommended PROM programmers and socket adapters of the HD4074459. Since an HMCS400-series instruction is ten bits long, the HMCS400-series MCU has a built-in conversion circuit to enable the use of a general-purpose PROM programmer. This circuit splits each instruction into five lower bits and five upper bits that are read from or written to consecutive addresses. This means that if, for example, 16 kwords of built-in PROM are to be programmed by a general-purpose PROM programmer, a 32-kbyte address space ($0000-$7FFF) must be specified. Warnings 1. Always specify addresses $0000 to $7FFF when programming with a PROM programmer. If address $8000 or higher is accessed, the PROM may not be programmed or verified correctly. Set all data in unused addresses to $FF. Note that the plastic-package versions cannot be erased or reprogrammed. 2. Make sure that the PROM programmer, socket adapter, and LSI are aligned correctly (their pin 1 positions match), otherwise overcurrents may damage the LSI. Before starting programming, make sure that the LSI is firmly fixed in the socket adapter and the socket adapter is firmly fixed onto the programmer. 3. PROM programmers have two voltages (VPP): 12.5 V and 21 V. Remember that ZTATTM devices require a VPP of 12.5 V--the 21-V setting will damage them. 12.5 V is the Intel 27256 setting. Programming and Verification The built-in PROM of the MCU can be program med at high speed without risk of voltage stress or damage to data reliability. Refer to table 30 for programming and verification modes. For details of PROM programming, refer to the preface section, Notes on PROM Programming. Table 30 PROM Mode Selection
Pin Mode Programming Verification Programming inhibited CE Low High High OE High Low High VPP VPP VPP VPP O0-O7 Data input Data output High impedance
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HD404459 Series
Table 31 Recommended PROM Programmers and Socket Adapters
Socket Adapter Model Name 121B PKW-1000 Package FP-64A FP-64A Model Name HS4459ESH01H HS4459ESH01H Manufacturer Hitachi Hitachi
PROM Programmer Manufacturer DATA I/O Corp. AVAL Corp.
VCC VCC RESET TEST M0 M1 O0 to O7 VPP VCC OSC1 R62 R63 R91 X1 GND HD4074459H A0 to A14 Address A0 to A14 Data O0 to O7 VCC
VPP
OE CE
OE CE
Figure 83 PROM Mode Connections
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HD404459 Series
Addressing Modes
RAM Addressing Modes The MCU has three RAM addressing modes (figure 84). Register Indirect Addressing Mode: The contents of the W, X, and Y registers (10 bits in total) are used for RAM addressing. Direct Addressing Mode: A direct addressing instruction consists of two words. The first word contains the opcode, and the contents of the second word (10 bits) are used for RAM addressing. Memory Register Addressing Mode: The memory registers (MR), which are located in 16 addresses from $040 to $04F, are accessed with the LAMR and XMRA instructions.
W register W1 W0 X3 X register X2 X1 X0 Y3 Y register Y2 Y 1 Y0
RAM address
AP9 AP8 AP7 AP6 AP5 AP4 AP3 AP2 AP1 AP0
Register Indirect Addressing
1st word of Instruction Opcode d
9
2nd word of Instruction d8 d7 d6 d5 d4 d3 d2 d1 d0
RAM address
AP9 AP8 AP7 AP6 AP5 AP4 AP3 AP2 AP1 AP0
Direct Addressing
Instruction Opcode 0 0 0 1 0 0 m3 m2 m1 m0
RAM address
AP9 AP8 AP7 AP6 AP5 AP4 AP3 AP2 AP1 AP0
Memory Register Addressing
Figure 84 RAM Addressing Modes
104
HD404459 Series
ROM Addressing Modes and the P Instruction The MCU has four ROM addressing modes (figure 85). Direct Addressing Mode: A program can branch to any address in ROM memory space by executing the JMPL, BRL, or CALL instruction. Each of these instructions replaces the 14 program counter bits (PC 13- PC0) with 14-bit immediate data. Current Page Addressing Mode: The MCU has 64 pages of ROM with 256 words per page. A program can branch to any address in the current page by executing the BR instruction. This instruction replaces the eight low-order bits of the program counter (PC7-PC0) with eight-bit immediate data. If the BR instruction is on a page boundary (address 256n + 255), executing that instruction transfers the PC contents to the next physical page (figure 87). This means that the execution of the BR instruction on a page boundary will make the program branch to the next page. Note that the HMCS400-series cross macroassembler has an automatic paging feature for ROM pages. Zero-Page Addressing Mode: A program can branch to the zero-page subroutine area located at $0000- $003F by executing the CAL instruction. When the CAL instruction is executed, 6 bits of immediate data are placed in the six low-order bits of the program counter (PC5-PC0), and 0s are placed in the eight highorder bits (PC13-PC6). Table Data Addressing Mode: A program can branch to an address determined by the contents of four-bit immediate data, the accumulator, and the B register by executing the TBR instruction. P Instruction: ROM data addressed in table data addressing mode can be referenced with the P instruction (figure 86). If bit 8 of the ROM data is 1, eight bits of ROM data are written to the accumulator and the B register. If bit 9 is 1, eight bits of ROM data are written to the R1 and R2 port output registers. If both bits 8 and 9 are 1, ROM data is written to the accumulator and the B register, and also to the R1 and R2 port output registers at the same time. The P instruction has no effect on the program counter.
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HD404459 Series
[JMPL] [BRL] [CALL] 1st word of instruction Opcode p3 p2 p1 p0 d9 d8 2nd word of instruction d7 d6 d5 d4 d3 d2 d1 d0
Program counter
PC13 PC12 PC11 PC10 PC 9 PC 8 PC 7 PC 6 PC 5 PC 4 PC 3 PC 2 PC 1 PC 0 Direct Addressing Instruction [BR] Opcode b7 b6 b5 b4 b3 b2 b1 b0
Program counter
PC13 PC12 PC11 PC10 PC 9 PC 8 PC7 PC 6 PC 5 PC 4 PC 3 PC 2 PC 1 PC 0 Current Page Addressing Instruction [CAL] 0 0 0 0 0 Opcode 0 0 0 a5 a4 a3 a2 a1 a0
Program counter
PC13 PC12 PC11 PC10 PC 9 PC 8 PC 7 PC 6 PC 5 PC 4 PC 3 PC 2 PC 1 PC 0 Zero Page Addressing Instruction
[TBR]
Opcode
p3
p2
p1
p0 B register B3 B2 B1 B0 A3 Accumulator A2 A1 A0
0 Program counter
0
PC13 PC12 PC11 PC10 PC 9 PC 8 PC 7 PC 6 PC 5 PC 4 PC 3 PC 2 PC 1 PC 0
Table Data Addressing
Figure 85 ROM Addressing Modes
106
HD404459 Series
Instruction [P] Opcode p3 p2 p1 p0 B3 0 0 B register B2 B1 B0 A3 Accumulator A2 A1 A0
Referenced ROM address RA13 RA12 RA11 RA10 RA 9 RA 8 RA 7 RA 6 RA 5 RA 4 RA 3 RA 2 RA 1 RA 0 Address Designation ROM data RO9 RO8 RO7 RO6 RO5 RO4 RO3 RO2 RO1 RO0
Accumulator, B register
B3
B2
B1
B0
A3 A
2
A1
A
0
If RO 8 = 1
ROM data
RO9 RO8 RO7 RO6 RO5 RO4 RO3 RO2 RO1 RO0
Output registers R1, R2
R2 3 R2 2 R21 R2 0 R1 3 R12 R11 R10 Pattern Output
If RO 9 = 1
Figure 86 P Instruction
256 (n - 1) + 255 BR AAA 256n
AAA
NOP
BR BR
AAA BBB
256n + 254 256n + 255 256 (n + 1)
BBB
NOP
Figure 87 Branching when the Branch Destination is on a Page Boundary
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HD404459 Series
Absolute Maximum Ratings (HD404458/HD404459)
Item Supply voltage Pin voltage Total permissible input current Total permissible output current Maximum input current Maximum output current Operating temperature Storage temperature Symbol VCC VT Io -Io Io -I o Topr Tstg Value -0.3 to +4.0 Unit V Notes
-0.3 to (VCC + 0.3) V 50 50 4 4 -20 to +75 -55 to +125 mA mA mA mA C C 2 3 4, 5 5, 6
Absolute Maximum Ratings (HD4074459)
Item Supply voltage Programming voltage Pin voltage Total permissible input current Total permissible output current Maximum input current Maximum output current Operating temperature Storage temperature Symbol VCC VPP VT Io -Io Io -I o Topr Tstg Value -0.3 to +4.0 -0.3 to +14.0 Unit V V 1 Notes
-0.3 to (VCC + 0.3) V 50 50 4 4 -20 to +75 -55 to +125 mA mA mA mA C C 2 3 4, 5 5, 6 7
Notes: Permanent damage may occur if these absolute maximum ratings are exceeded. Normal operation must be under the conditions stated in the electrical characteristics tables. If these conditions are exceeded, the LSI may malfunction or its reliability may be affected. 1. Applies to D 10 (VPP) of the HD4074459. 2. The total permissible input current is the total of input currents simultaneously flowing in from all the I/O pins to ground. 3. The total permissible output current is the total of output currents simultaneously flowing out from VCC to all I/O pins. 4. The maximum input current is the maximum current flowing from each I/O pin to ground. 5. Applies to D0-D 9, R0-R8, and R90-R9 2. 6. The maximum output current is the maximum current flowing out from V CC to each I/O pin. 7. Depends on the supply voltage.
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HD404459 Series
Electrical Characteristics
DC Characteristics HD404458, HD404459: VCC = 1.8 to 3.6 V, GND = 0 V, Ta = -20 to +75C, f OSC = 0.4 to 4.0 MHz HD4074459: VCC = 2.2 to 2.7 V, GND = 0 V, Ta = -5 to +60C, f OSC = 0.4 to 2.0 MHz; VCC = 2.7 to 3.6 V, GND = 0 V, Ta = -20 to +75C, f OSC = 0.4 to 4.0 MHz, unless otherwise specified.
Item Input high voltage Symbol Pin(s) VIH RESET, STOPC, INT0, INT1, INT2, INT3, SCK, SI, WU0-WU7, EVNB, EVND OSC 1 Input low voltage VIL RESET, STOPC, INT0, INT1, INT2, INT3, SCK, SI, WU0-WU7, EVNB, EVND OSC 1 Output high VOH voltage Output low VOL voltage I/O leakage | IIL | current SCK, SO, TOB, TOC, TOD SCK, SO, TOB, TOC, TOD RESET, STOPC, INT0, INT1, INT2, INT3, SCK, SI, WU0-WU7, SO, EVNB, EVND, OSC 1, TOB, TOC, TOD Current dissipation in active mode I CC VCC -- 3 6 mA HD404458, HD404459: VCC = 3.0 V, f OSC = 4 MHz -- 5 9 mA HD4074459: VCC = 3.0 V, f OSC = 4 MHz 2 2 -- -- 1.0 A Vin = 0 V to VCC 1 -- -- 0.4 V I OL = 0.4 mA -0.3 -- 0.3 -- V V External clock operation -I OH = 0.3 mA VCC - 0.3 -- -0.3 -- VCC + 0.3 V 0.1V CC V External clock operation -- Min 0.9V CC Typ -- Max Unit Test Condition -- Notes
VCC + 0.3 V
VCC - 0.5 --
109
HD404459 Series
Item Current dissipation in standby mode Symbol Pin(s) I SBY VCC Min -- Typ 1.2 Max 3 Unit mA Test Condition VCC = 3.0 V, f OSC = 4 MHz A Notes 3
I SUB Current dissipation in subactive mode
VCC
--
35
70
HD404458, HD404459: VCC = 3.0 V, 32-kHz oscillator
--
70
150
A
HD4074459: VCC = 3.0 V, 32-kHz oscillator
Current dissipation in watch mode Current dissipation in stop mode
I WTC
VCC
--
8
15
A
VCC = 3.0 V, 32-kHz oscillator
4
I STOP
VCC
--
1
10
A
VCC = 3.0 V, no 32-kHz oscillator
4
Stop mode VSTOP retaining voltage
VCC
1.5
--
--
V
No 32-kHz oscillator 5
Notes: 1. Output buffer current is excluded. 2. I CC is the source current when no I/O current is flowing while the MCU is in reset state. Test conditions: MCU: Reset Pins: RESET at V CC (0.9VCC to VCC) TEST at V CC (0.9VCC to VCC) 3. I SBY is the source current when no I/O current is flowing while the MCU timer is operating. Test conditions: MCU: I/O reset Serial interface stopped Standby mode Pins: RESET at GND (0 V to 0.3 V) TEST at V CC (0.9VCC to VCC) 4. These are the source currents when no I/O current is flowing. Test conditions: Pins: RESET at GND (0 V to 0.3 V) TEST at V CC (0.9VCC to VCC) D10* at VCC (0.9VCC to VCC) Note: * Applies to HD4074459 5. RAM data retention is the voltage required for retaining RAM data.
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HD404459 Series
I/O Characteristics for Standard Pins HD404458, HD404459: VCC = 1.8 to 3.6 V, GND = 0 V, Ta = -20 to +75C, f OSC = 0.4 to 4.0 MHz HD4074459: VCC = 2.2 to 2.7 V, GND = 0 V, Ta = -5 to +60C, f OSC = 0.4 to 2.0 MHz; VCC = 2.7 to 3.6 V, GND = 0 V, Ta = -20 to +75C, f OSC = 0.4 to 4.0 MHz, unless otherwise specified.
Item Symbol Pin(s) D0-D 11 , R0-RA Input low voltage VIL VOH D0-D 11 , R0-RA Output high voltage D0-D 9, R0-R8, R9 0-R9 2 Output low voltage VOL D0-D 9, R0-R8, R9 0-R9 2 I/O leakage current | IIL | D0-D 11 , R0-RA A A A A -- -- 1 A HD404458, HD404459: Vin = 0 V to VCC D0-D 9, D11, -- R0-RA D10 -- -- 1 -- 1 HD4074459: Vin = 0 V to VCC HD4074459: Vin = VCC - 0.3 to V CC -- -- 20 HD4074459: Vin = 0 V to 0.3 V Pull-up MOS current -I PU D0-D 9, R0-R8, R9 0-R9 2 Note: 1. Output buffer current is excluded. 5 40 90 VCC = 3.0 V, Vin = 0 V 1 1 1 1 -- -- 0.4 V I OL = 0.4 mA VCC - 0.5 -- -- V -I OH = 0.3 mA -0.3 -- 0.3V CC V -- Min 0.7V CC Typ -- Max Unit Test Condition -- Note
Input high voltage VIH
VCC + 0.3 V
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HD404459 Series
Voltage Comparator Characteristics HD404458, HD404459: VCC = 2.0 to 3.6 V, GND = 0 V, Ta = -10 to +75C, f OSC = 0.4 to 4.0 MHz HD4074459: VCC = 2.2 to 2.7 V, GND = 0 V, Ta = -5 to +60C, f OSC = 0.4 to 2.0 MHz; VCC = 2.7 to 3.6 V, GND = 0 V, Ta = -10 to +75C, f OSC = 0.4 to 4.0 MHz,unless otherwise specified.
Item Symbol Pin(s) COMP0- COMP3 COMP0- COMP3 VC ref Min Vref + 0.17 -- 0 Typ -- -- -- Max -- Vref - 0.03 VCC Unit V V V Test Condition -- -- -- Note 1 1
Input high voltage VIHA Input low voltage Analog input standard voltage range Note: VILA VC ref
1. When an internal reference voltage is selected, the standard voltage is an expected voltage of internal Vref specified by the comparator control register (CCR).
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HD404459 Series
AC Characteristics HD404458, HD404459: VCC = 1.8 to 3.6 V, GND = 0 V, Ta = -20 to +75C, f OSC = 0.4 to 4.0 MHz HD4074459: VCC = 2.2 to 2.7 V, GND = 0 V, Ta = -5 to +60C, f OSC = 0.4 to 2.0 MHz; VCC = 2.7 to 3.6 V, GND = 0 V, Ta = -20 to +75C, f OSC = 0.4 to 4.0 MHz, unless otherwise specified.
Item Clock oscillation frequency Symbol f OSC Pin(s) OSC 1, OSC 2 Min 0.4 Typ -- Max 4.0 Unit MHz Test Condition HD404458, HD404459: 1/4division, VCC = 1.8 V to 3.6 V HD4074459: 1/4 division, VCC = 2.7 V to 3.6 V 0.4 -- 2.0 MHz HD4074459: 1/4 division, VCC = 2.2 V to 2.7 V X1, X2 Instruction cycle time t cyc -- -- 1.0 32.768 -- -- 10 kHz s -- HD404458, HD404459: 1/4 division, VCC = 1.8 V to 3.6 V HD4074459: 1/4 division, VCC = 2.7 V to 3.6 V 2.0 -- 10 s HD4074459: 1/4 division, VCC = 2.2 V to 2.7 V t subcyc -- -- 244.14 -- s s ms 32-kHz oscillator, 1/8 division -- 122.07 -- 32-kHz oscillator, 1/4 division Oscillation t RC stabilization time (ceramic oscillator) Oscillation stabilization time (crystal oscillator) t RC OSC 1, OSC 2 -- -- 60 -- 1 Notes
OSC 1, OSC 2
--
--
60
ms
--
1
X1, X2 External clock high t CPH width External clock low t CPL width OSC 1 OSC 1
-- 105 105
-- -- --
3 -- --
s ns ns
Ta = -10C to+60C f OSC = 4 MHz f OSC = 4 MHz
2 3 3
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HD404459 Series
Item Symbol Pin(s) OSC 1 OSC 1 INT0-INT3, WU0-WU7, EVNB, EVND INT0-INT3, WU0-WU7, EVNB, EVND RESET STOPC RESET STOPC 2 1 -- -- -- -- -- -- -- -- -- -- 20 20 15 15 t cyc t RC ms ms pF pF -- -- -- -- f = 1 MHz, Vin = 0 V HD404458, HD404459: f = 1MHz, Vin = 0 V -- -- 180 pF HD4074459: f = 1 MHz, Vin = 0 V Notes: 1. The oscillation stabilization time is the period required for the oscillator to stabilize after V CC reaches 1.8 V (2.2 V: HD4074459) at power-on, or after RESET input goes high or STOPC input goes low when stop mode is cancelled. At power-on or when stop mode is cancelled, RESET or STOPC must be input for at least tRC to ensure the oscillation stabilization time. If using a ceramic or crystal oscillator, contact its manufacturer to determine the required stabilization time, since it will depend on the circuit constants and stray capacitances. Set bits 0 and 1 (MIS0, MIS1) of the miscellaneous register (MIS: $00C) according to the oscillation stabilization time of the system oscillation. 2. The oscillation stabilization time is the period required for the oscillator to stabilize after V CC reaches 1.8 V (2.2 V: HD4074459) at power-on, or after RESET input goes high or STOPC input goes low when stop mode is cancelled. If using a crystal oscillator, contact its manufacturer to determine the required stabilization time, since it will depend on the circuit constants and stray capacitances. 3. Refer to figure 88. 4. Refer to figure 89. The t cyc unit applies when the MCU is in standby or active mode. The tsubcyc unit applies when the MCU is in watch or subactive mode. 5. Refer to figure 90. 6. Refer to figure 91. 7. In watch or subactive mode, the periods when the INT0 and WU0-WU7 signals are high and when these signals are low must be equal to the interrupt frame period or longer. 5 6 5 6 2 -- -- t cyc / t subcyc -- 4, 7 Min -- -- 2 Typ -- -- -- Max 20 20 -- Unit ns ns t cyc / t subcyc Test Condition -- -- -- Notes 3 3 4, 7 External clock rise t CPr time External clock fall time t CPf
INT0-INT3, EVNB, t IH WU0-WU7, EVND high widths INT0-INT3, EVNB, t IL WU0-WU7, EVND low widths RESET high width t RSTH STOPC low width RESET fall time STOPC rise time Input capacitance t STPL t RSTf t STPr Cin
All pins except -- for D10 D10 --
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HD404459 Series
Serial Interface Timing Characteristics HD404458, HD404459: VCC = 1.8 to 3.6 V, GND = 0 V, Ta = -20 to +75C, f OSC = 0.4 to 4.0 MHz HD4074459: VCC = 2.2 to 2.7 V, GND = 0 V, Ta = -5 to +60C, f OSC = 0.4 to 2.0 MHz; VCC = 2.7 to 3.6 V, GND = 0 V, Ta = -20 to +75C, f OSC = 0.4 to 4.0 MHz, unless otherwise specified. During Transmit Clock Output
Item Transmit clock cycle time Transmit clock high width Transmit clock low width Symbol t Scyc t SCKH t SCKL Pin SCK SCK SCK SCK SCK SO SI SI Min 1.0 0.4 0.4 -- -- -- 300 300 Typ -- -- -- -- -- -- -- -- Max -- -- -- 200 200 500 -- -- Unit t cyc t Scyc t Scyc ns ns ns ns ns Test Condition Load shown in figure 93 Load shown in figure 93 Load shown in figure 93 Load shown in figure 93 Load shown in figure 93 Load shown in figure 93 -- -- Note 1 1 1 1 1 1 1 1
Transmit clock rise time t SCKr Transmit clock fall time t SCKf
Serial output data delay t DSO time Serial input data setup time Serial input data hold time Note: t SSI t HSI
1. Refer to figure 92.
During Transmit Clock Input
Item Transmit clock cycle time Transmit clock high width Transmit clock low width Symbol t Scyc t SCKH t SCKL Pin SCK SCK SCK SCK SCK SO SI SI Min 1.0 0.4 0.4 -- -- -- 300 300 Typ -- -- -- -- -- -- -- -- Max -- -- -- 200 200 500 -- -- Unit t cyc t Scyc t Scyc ns ns ns ns ns Test Condition -- -- -- -- -- Load shown in figure 93 -- -- Note 1 1 1 1 1 1 1 1
Transmit clock rise time t SCKr Transmit clock fall time t SCKf
Serial output data delay t DSO time Serial input data setup time Serial input data hold time Note: t SSI t HSI
1. Refer to figure 92.
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HD404459 Series
OSC1
1/fCP VCC - 0.3 V 0.3 V tCPr tCPH tCPf tCPL
Figure 88 External Clock Timing
WU0 to WU7, INT0 to INT3, EVNB, EVND
0.9VCC 0.1VCC
tIH
tIL
Figure 89 Interrupt Timing
RESET
0.9VCC 0.1VCC
tRSTH
tRSTf
Figure 90 Reset Timing
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HD404459 Series
STOPC
0.9VCC 0.1VCC
tSTPL
tSTPr
Figure 91 STOPC Timing
t Scyc t SCKf SCK VCC - 0.5 V (0.9VCC )* 0.4 V (0.1VCC)* t DSO SO VCC - 0.5 V 0.4 V t SSI SI 0.9V CC 0.1VCC t HSI t SCKL t SCKH t SCKr
Note: * VCC - 0.5 V and 0.4 V are the threshold voltages for transmit clock output, and 0.9VCC and 0.1VCC are the threshold voltages for transmit clock input.
Figure 92 Serial Interface Timing
VCC RL = 2.6 k Test point C= 30 pF R= 12 k 1S2074 H or equivalent
Figure 93 Timing Load Circuit
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HD404459 Series
Notes on ROM Out
Please pay attention to the following items regarding ROM out. On ROM out, fill the ROM area indicated below with 1s to create the same data size as a 16-kword version (HD404459). A 16-kword data size is required to change ROM data to mask manufacturing data since the program used is for a 16-kword version. This limitation applies when using an EPROM or a data base.
ROM 8-kword version: HD404458 Address $2000-$3FFF
$0000 Vector address $000F $0010 Zero-page subroutine (64 words) $003F $0040 Pattern & program (8,192 words) $1FFF $2000 Not used $3FFF Fill this area with 1s
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HD404459 Series
HD404458, HD404459 Option List
Please check off the appropriate applications and enter the necessary information.
Date of order Customer 1. ROM size HD404458 HD404459 2. Optional Functions * * With 32-kHz CPU operation, with time-base for clock Without 32-kHz CPU operation, with time-base for clock Without 32-kHz CPU operation, without time-base Note: * Options marked with an asterisk require a subsystem crystal oscillator (X1, X2). 3. ROM code media Please specify the first type listed below (the upper bits and lower bits are mixed together), when using the EPROM on-package microcomputer type (including ZTATTM version). EPROM: The upper bits and lower bits are mixed together. The upper five bits and lower five bits are programmed to the same EPROM in alternating order (i.e., LULULU...). EPROM: The upper bits and lower bits are separated. The upper five bits and lower five bits are programmed to different EPROMS. 8-kword 16-kword Department Name ROM code name LSI number
4. Oscillator for OSC1 and OSC2 Ceramic oscillator Crystal oscillator External clock f= f= f= MHz MHz MHz
5. Stop mode Used Not used
6. Package FP-64A
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HD404459 Series
Cautions
1. Hitachi neither warrants nor grants licenses of any rights of Hitachi's or any third party's patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with third party's rights, including intellectual property rights, in connection with use of the information contained in this document. 2. Products and product specifications may be subject to change without notice. Confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However, contact Hitachi's sales office before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as failsafes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the Hitachi product. 5. This product is not designed to be radiation resistant. 6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from Hitachi. 7. Contact Hitachi's sales office for any questions regarding this document or Hitachi semiconductor products.
Copyright (c) Hitachi, Ltd., 1998. All rights reserved. Printed in Japan.
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